Lines Matching refs:isZExt
161 bool WantResult = true, bool IsZExt = false);
181 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
182 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
189 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
190 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
193 bool IsZExt = false);
197 bool IsZExt = false);
221 uint64_t Imm, bool IsZExt = true);
225 uint64_t Imm, bool IsZExt = true);
229 uint64_t Imm, bool IsZExt = false);
271 bool IsZExt = isa<ZExtInst>(I);
278 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr()))
1013 /*IsZExt=*/true);
1017 /*IsZExt=*/false);
1091 bool WantResult, bool IsZExt) {
1102 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB;
1106 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH;
1139 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
1143 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue();
1237 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
1406 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) {
1421 return emitICmp(VT, LHS, RHS, IsZExt);
1429 bool IsZExt) {
1431 IsZExt) != 0;
1476 bool SetFlags, bool WantResult, bool IsZExt) {
1478 IsZExt);
1506 bool SetFlags, bool WantResult, bool IsZExt) {
1508 IsZExt);
2252 SrcReg = emitIntExt(VT, SrcReg, MVT::i32, /*IsZExt=*/true);
2769 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
2935 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
2945 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
3712 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
3715 bool IsZExt = Outs[0].Flags.isZExt();
3716 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
3802 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
3810 if (IsZExt) {
3903 bool IsZExt) {
3928 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
3967 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4010 bool IsZExt) {
4035 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4067 if (Shift >= SrcBits && IsZExt)
4072 if (!IsZExt) {
4073 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4079 IsZExt = true;
4088 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4118 Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
4131 bool IsZExt) {
4156 return emitIntExt(SrcVT, Op0, RetVT, IsZExt);
4188 if (Shift >= SrcBits && IsZExt)
4197 unsigned Opc = OpcTable[IsZExt][Is64Bit];
4212 bool IsZExt) {
4232 return emiti1Ext(SrcReg, DestVT, IsZExt);
4235 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4237 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4242 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4244 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
4249 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
4337 bool IsZExt = isa<ZExtInst>(I);
4345 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI)))
4354 if (IsZExt) {
4394 bool IsZExt = isa<ZExtInst>(I);
4396 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
4419 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4492 bool IsZExt = true;
4498 IsZExt = true;
4507 IsZExt = false;
4519 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt);
4558 bool IsZExt = I->getOpcode() != Instruction::AShr;
4565 IsZExt = true;
4574 IsZExt = false;
4588 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4591 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4594 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);
4797 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*IsZExt=*/false);
