Lines Matching full:aarch64
1 //===- AArch64FrameLowering.cpp - AArch64 Frame Lowering -------*- C++ -*-====//
10 // This file contains the AArch64 implementation of TargetFrameLowering class.
12 // On AArch64, stack frames are structured as follows:
112 static cl::opt<bool> EnableRedZone("aarch64-redzone",
113 cl::desc("enable use of redzone on AArch64"),
192 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, Amount, TII);
198 emitFrameOffset(MBB, I, DL, AArch64::SP, AArch64::SP, -CalleePopAmount,
239 if (HasFP && (FramePtr == Reg || Reg == AArch64::LR)) {
257 assert(((MBBI->getOpcode() == AArch64::STPXpre ||
258 MBBI->getOpcode() == AArch64::STPDpre) &&
259 MBBI->getOperand(3).getReg() == AArch64::SP &&
272 return MBBI->getOpcode() == AArch64::STPXi ||
273 MBBI->getOpcode() == AArch64::STPDi ||
274 MBBI->getOpcode() == AArch64::STPXpre ||
275 MBBI->getOpcode() == AArch64::STPDpre;
313 emitFrameOffset(MBB, MBBI, DL, AArch64::SP, AArch64::SP, -NumBytes, TII,
345 emitFrameOffset(MBB, MBBI, DL, AArch64::FP, AArch64::SP, FPOffset, TII,
356 unsigned scratchSPReg = AArch64::SP;
359 scratchSPReg = AArch64::X9;
367 emitFrameOffset(MBB, MBBI, DL, scratchSPReg, AArch64::SP, -NumBytes, TII,
373 assert(scratchSPReg != AArch64::SP);
387 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ANDXri), AArch64::SP)
400 TII->copyPhysReg(MBB, MBBI, DL, RegInfo->getBaseRegister(), AArch64::SP,
484 unsigned LR = RegInfo->getDwarfRegNum(AArch64::LR, true);
523 case AArch64::LDPXpost:
524 case AArch64::LDPDpost:
527 case AArch64::LDPXi:
528 case AArch64::LDPDi:
531 MI.getOperand(RtIdx + 2).getReg() != AArch64::SP)
550 IsTailCallReturn = RetOpcode == AArch64::TCRETURNdi ||
551 RetOpcode == AArch64::TCRETURNri;
628 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::SP, NumBytes,
638 emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::FP,
705 FrameReg = AArch64::SP;
717 if (Reg != AArch64::LR)
721 bool LRLiveIn = MF.getRegInfo().isLiveIn(AArch64::LR);
760 if (AArch64::GPR64RegClass.contains(Reg1)) {
761 assert(AArch64::GPR64RegClass.contains(Reg2) &&
765 StrOpc = AArch64::STPXpre;
767 StrOpc = AArch64::STPXi;
768 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
769 assert(AArch64::FPR64RegClass.contains(Reg2) &&
773 StrOpc = AArch64::STPDpre;
775 StrOpc = AArch64::STPDi;
787 if (StrOpc == AArch64::STPDpre || StrOpc == AArch64::STPXpre)
788 MIB.addReg(AArch64::SP, RegState::Define);
794 .addReg(AArch64::SP)
833 if (AArch64::GPR64RegClass.contains(Reg1)) {
834 assert(AArch64::GPR64RegClass.contains(Reg2) &&
837 LdrOpc = AArch64::LDPXpost;
839 LdrOpc = AArch64::LDPXi;
840 } else if (AArch64::FPR64RegClass.contains(Reg1)) {
841 assert(AArch64::FPR64RegClass.contains(Reg2) &&
844 LdrOpc = AArch64::LDPDpost;
846 LdrOpc = AArch64::LDPDi;
859 if (LdrOpc == AArch64::LDPXpost || LdrOpc == AArch64::LDPDpost)
860 MIB.addReg(AArch64::SP, RegState::Define);
864 .addReg(AArch64::SP)
888 SavedRegs.set(AArch64::FP);
889 SavedRegs.set(AArch64::LR);
898 SavedRegs.set(AArch64::X9);
914 assert((AArch64::GPR64RegClass.contains(OddReg) &&
915 AArch64::GPR64RegClass.contains(EvenReg)) ^
916 (AArch64::FPR64RegClass.contains(OddReg) &&
917 AArch64::FPR64RegClass.contains(EvenReg)) &&
926 if (AArch64::GPR64RegClass.contains(OddReg)) {
936 unsigned Reg = AArch64::NoRegister;
948 assert(((OddReg == AArch64::LR && EvenReg == AArch64::FP) ||
952 if (AArch64::GPR64RegClass.contains(OddReg)) {
958 if (Reg != AArch64::NoRegister && !RegInfo->isReservedReg(MF, Reg))
1005 const TargetRegisterClass *RC = &AArch64::GPR64RegClass;