Lines Matching defs:CSel
741 case AArch64ISD::CSEL: {
843 case AArch64ISD::CSEL: return "AArch64ISD::CSEL";
1678 // (csel x, (xor x, -1), cc ...)
1717 return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
1779 Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,
3853 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);
3859 // If that fails, we'll need to perform an FCMP + CSEL sequence. Go ahead
3872 return DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);
3876 // this case, we emit the first CSEL and then emit a second using the output
3882 DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
3885 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
3917 unsigned Opcode = AArch64ISD::CSEL;
3934 // with a CSINV rather than a CSEL.
3942 // that we can match with a CSNEG rather than a CSEL.
3955 // instead of a CSEL in that case.
3992 if (Opcode != AArch64ISD::CSEL) {
4017 SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);
4019 // If we need a second CSEL, emit it, using the output of the first as the
4023 return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);
4026 // Otherwise, return the output of the first CSEL.
4063 return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
4412 // is "undef". We wanted 0, so CSEL it directly.
4417 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
4431 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
4442 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
4468 // is "undef". We wanted 0, so CSEL it directly.
4473 DAG.getNode(AArch64ISD::CSEL, dl, VT, DAG.getConstant(0, dl, MVT::i64),
4487 SDValue Hi = DAG.getNode(AArch64ISD::CSEL, dl, VT, HiForBigShift,
4494 SDValue Lo = DAG.getNode(AArch64ISD::CSEL, dl, VT, LoForBigShift,
7337 // Generate SUBS and CSEL for integer abs.
7346 // and change it to SUB and CSEL.
7354 // Generate SUBS & CSEL.
7358 return DAG.getNode(AArch64ISD::CSEL, DL, VT, N0.getOperand(0), Neg,
7395 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7400 Created->push_back(CSel.getNode());
7405 DAG.getNode(ISD::SRA, DL, VT, CSel, DAG.getConstant(Lg2, DL, MVT::i64));
8117 // Otherwise, check if this is a matching csel instruction.
8119 // - csel 1, 0, cc
8120 // - csel 0, 1, !cc
8121 if (Op.getOpcode() != AArch64ISD::CSEL)
8124 // TODO: we want the operands of the Cmp not the csel
8161 // (csel x, (add x, 1), !cc ...)
8200 return DAG.getNode(AArch64ISD::CSEL, dl, VT, RHS, LHS, CCVal, Cmp);
9648 case AArch64ISD::CSEL:
