Lines Matching refs:Legal
147 // Virtually no operation on f128 is legal, but LLVM can't expand them when
391 setOperationAction(ISD::FFLOOR, Ty, Legal);
392 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
393 setOperationAction(ISD::FCEIL, Ty, Legal);
394 setOperationAction(ISD::FRINT, Ty, Legal);
395 setOperationAction(ISD::FTRUNC, Ty, Legal);
396 setOperationAction(ISD::FROUND, Ty, Legal);
397 setOperationAction(ISD::FMINNUM, Ty, Legal);
398 setOperationAction(ISD::FMAXNUM, Ty, Legal);
399 setOperationAction(ISD::FMINNAN, Ty, Legal);
400 setOperationAction(ISD::FMAXNAN, Ty, Legal);
408 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
421 // Make floating-point constants legal for the large code model, so they don't
424 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
425 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
453 setIndexedLoadAction(im, MVT::i8, Legal);
454 setIndexedLoadAction(im, MVT::i16, Legal);
455 setIndexedLoadAction(im, MVT::i32, Legal);
456 setIndexedLoadAction(im, MVT::i64, Legal);
457 setIndexedLoadAction(im, MVT::f64, Legal);
458 setIndexedLoadAction(im, MVT::f32, Legal);
459 setIndexedLoadAction(im, MVT::f16, Legal);
460 setIndexedStoreAction(im, MVT::i8, Legal);
461 setIndexedStoreAction(im, MVT::i16, Legal);
462 setIndexedStoreAction(im, MVT::i32, Legal);
463 setIndexedStoreAction(im, MVT::i64, Legal);
464 setIndexedStoreAction(im, MVT::f64, Legal);
465 setIndexedStoreAction(im, MVT::f32, Legal);
466 setIndexedStoreAction(im, MVT::f16, Legal);
470 setOperationAction(ISD::TRAP, MVT::Other, Legal);
528 // FIXME: v1f64 shouldn't be legal if we can avoid it, because it leads to
593 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
617 setOperationAction(ISD::FFLOOR, Ty, Legal);
618 setOperationAction(ISD::FNEARBYINT, Ty, Legal);
619 setOperationAction(ISD::FCEIL, Ty, Legal);
620 setOperationAction(ISD::FRINT, Ty, Legal);
621 setOperationAction(ISD::FTRUNC, Ty, Legal);
622 setOperationAction(ISD::FROUND, Ty, Legal);
673 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
698 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
704 setOperationAction(Opcode, VT.getSimpleVT(), Legal);
709 setIndexedLoadAction(im, VT.getSimpleVT(), Legal);
710 setIndexedStoreAction(im, VT.getSimpleVT(), Legal);
776 // this as those are legal types and will be handled by isel directly.
1727 // Let legalize expand this if it isn't a legal type yet.
1761 // Let legalize expand this if it isn't a legal type yet.
1830 // It's legal except when f128 is involved
1897 // It's legal except when f128 is involved
1957 // Other conversions are legal, unless it's to the completely software-based
2095 // Element types smaller than 32 bits are not legal, so use i32 elements.
2143 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
2178 // Fall through to expand this. It is not legal.
2181 // Other vector multiplications are legal.
3089 // promoted to a legal register type i32, we should truncate Arg back to
3607 // Only lower legal XALUO ops.
4054 // Only lower legal XALUO ops.
6365 // Insertion/extraction are legal for V128 types.
6399 // Insertion/extraction are legal for V128 types.
7184 // 12-bit optionally shifted immediates are legal for adds.
7200 /// by AM is legal for this target, for a load/store of the specified type.
7827 // legal vector types and such.
7930 // legal vector types and such.
7974 // legal vector types and such.
8353 // the intrinsics must be legal and take an i32, this means there's almost
8458 // Type legalization will split an extend of a small, legal, type to a larger
8483 // We're only interested in cleaning things up for non-legal vector types
8484 // here. If both the source and destination are legal, things will just
9284 // legal instead.
9552 // There are no legal vectors of i1, so this would be pointless.
9929 // Since i128 isn't legal and intrinsics don't get type-lowered, the ldrexd
9971 // Since the intrinsics must have legal
