Lines Matching full:b00
436 defm MOVN : MoveImmediate<0b00, "movn">;
689 defm LSLV : Shift<0b00, "lsl", shl>;
753 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_aarch64_crc32b, "crc32b">;
758 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_aarch64_crc32cb, "crc32cb">;
838 defm AND : LogicalImm<0b00, "and", and, "bic">;
855 defm AND : LogicalReg<0b00, 0, "and", and>;
856 defm BIC : LogicalReg<0b00, 1, "bic",
957 defm SBFM : BitfieldImm<0b00, "sbfm">;
1064 defm CSEL : CondSelect<0, 0b00, "csel">;
1068 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
1217 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1221 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1236 defm LDPW : LoadPairOffset<0b00, 0, GPR32, simm7s4, "ldp">;
1238 defm LDPS : LoadPairOffset<0b00, 1, FPR32, simm7s4, "ldp">;
1245 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1247 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1254 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1256 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1264 defm LDNPW : LoadPairNoAlloc<0b00, 0, GPR32, simm7s4, "ldnp">;
1266 defm LDNPS : LoadPairNoAlloc<0b00, 1, FPR32, simm7s4, "ldnp">;
1275 defm LDRBB : Load8RO<0b00, 0, 0b01, GPR32, "ldrb", i32, zextloadi8>;
1281 defm LDRB : Load8RO<0b00, 1, 0b01, FPR8, "ldr", untyped, load>;
1285 defm LDRQ : Load128RO<0b00, 1, 0b11, FPR128, "ldr", f128, load>;
1292 defm LDRSBW : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb", i32, sextloadi8>;
1293 defm LDRSBX : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb", i64, sextloadi8>;
1453 defm LDRB : LoadUI<0b00, 1, 0b01, FPR8, uimm12s1, "ldr",
1465 defm LDRQ : LoadUI<0b00, 1, 0b11, FPR128, uimm12s16, "ldr",
1549 defm LDRBB : LoadUI<0b00, 0, 0b01, GPR32, uimm12s1, "ldrb",
1592 defm LDRSBW : LoadUI<0b00, 0, 0b11, GPR32, uimm12s1, "ldrsb",
1596 defm LDRSBX : LoadUI<0b00, 0, 0b10, GPR64, uimm12s1, "ldrsb",
1621 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1623 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1642 defm LDURB : LoadUnscaled<0b00, 1, 0b01, FPR8, "ldur",
1654 defm LDURQ : LoadUnscaled<0b00, 1, 0b11, FPR128, "ldur",
1663 : LoadUnscaled<0b00, 0, 0b01, GPR32, "ldurb",
1803 : LoadUnscaled<0b00, 0, 0b11, GPR32, "ldursb",
1807 : LoadUnscaled<0b00, 0, 0b10, GPR64, "ldursb",
1844 defm LDTRB : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1851 defm LDTRSBW : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1852 defm LDTRSBX : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1861 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1865 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1872 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1873 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1876 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1886 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1890 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1897 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1898 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1901 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1913 defm STPW : StorePairOffset<0b00, 0, GPR32, simm7s4, "stp">;
1915 defm STPS : StorePairOffset<0b00, 1, FPR32, simm7s4, "stp">;
1920 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, simm7s4, "stp">;
1922 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, simm7s4, "stp">;
1927 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1929 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1934 defm STNPW : StorePairNoAlloc<0b00, 0, GPR32, simm7s4, "stnp">;
1936 defm STNPS : StorePairNoAlloc<0b00, 1, FPR32, simm7s4, "stnp">;
1944 defm STRBB : Store8RO< 0b00, 0, 0b00, GPR32, "strb", i32, truncstorei8>;
1945 defm STRHH : Store16RO<0b01, 0, 0b00, GPR32, "strh", i32, truncstorei16>;
1946 defm STRW : Store32RO<0b10, 0, 0b00, GPR32, "str", i32, store>;
1947 defm STRX : Store64RO<0b11, 0, 0b00, GPR64, "str", i64, store>;
1951 defm STRB : Store8RO< 0b00, 1, 0b00, FPR8, "str", untyped, store>;
1952 defm STRH : Store16RO<0b01, 1, 0b00, FPR16, "str", f16, store>;
1953 defm STRS : Store32RO<0b10, 1, 0b00, FPR32, "str", f32, store>;
1954 defm STRD : Store64RO<0b11, 1, 0b00, FPR64, "str", f64, store>;
1955 defm STRQ : Store128RO<0b00, 1, 0b10, FPR128, "str", f128, store>;
2045 defm STRX : StoreUI<0b11, 0, 0b00, GPR64, uimm12s8, "str",
2048 defm STRW : StoreUI<0b10, 0, 0b00, GPR32, uimm12s4, "str",
2051 defm STRB : StoreUI<0b00, 1, 0b00, FPR8, uimm12s1, "str",
2054 defm STRH : StoreUI<0b01, 1, 0b00, FPR16, uimm12s2, "str",
2057 defm STRS : StoreUI<0b10, 1, 0b00, FPR32, uimm12s4, "str",
2060 defm STRD : StoreUI<0b11, 1, 0b00, FPR64, uimm12s8, "str",
2063 defm STRQ : StoreUI<0b00, 1, 0b10, FPR128, uimm12s16, "str", []>;
2065 defm STRHH : StoreUI<0b01, 0, 0b00, GPR32, uimm12s2, "strh",
2069 defm STRBB : StoreUI<0b00, 0, 0b00, GPR32, uimm12s1, "strb",
2144 defm STURX : StoreUnscaled<0b11, 0, 0b00, GPR64, "stur",
2147 defm STURW : StoreUnscaled<0b10, 0, 0b00, GPR32, "stur",
2150 defm STURB : StoreUnscaled<0b00, 1, 0b00, FPR8, "stur",
2153 defm STURH : StoreUnscaled<0b01, 1, 0b00, FPR16, "stur",
2156 defm STURS : StoreUnscaled<0b10, 1, 0b00, FPR32, "stur",
2159 defm STURD : StoreUnscaled<0b11, 1, 0b00, FPR64, "stur",
2162 defm STURQ : StoreUnscaled<0b00, 1, 0b10, FPR128, "stur",
2165 defm STURHH : StoreUnscaled<0b01, 0, 0b00, GPR32, "sturh",
2168 defm STURBB : StoreUnscaled<0b00, 0, 0b00, GPR32, "sturb",
2257 defm STTRW : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
2258 defm STTRX : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
2260 defm STTRH : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
2261 defm STTRB : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
2265 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str", pre_store, i32>;
2266 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str", pre_store, i64>;
2267 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str", pre_store, untyped>;
2268 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str", pre_store, f16>;
2269 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str", pre_store, f32>;
2270 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str", pre_store, f64>;
2271 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str", pre_store, f128>;
2273 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb", pre_truncsti8, i32>;
2274 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh", pre_truncsti16, i32>;
2319 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str", post_store, i32>;
2320 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str", post_store, i64>;
2321 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str", post_store, untyped>;
2322 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str", post_store, f16>;
2323 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str", post_store, f32>;
2324 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str", post_store, f64>;
2325 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str", post_store, f128>;
2327 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb", post_truncsti8, i32>;
2328 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh", post_truncsti16, i32>;
2377 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2382 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2387 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2392 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2397 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2402 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2421 def LDLARB : LoadAcquire <0b00, 1, 1, 0, 0, GPR32, "ldlarb">;
2427 def STLLRB : StoreRelease <0b00, 1, 0, 0, 0, GPR32, "stllrb">;
2435 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_aarch64_neon_fcvtas>;
2436 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_aarch64_neon_fcvtau>;
2439 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_aarch64_neon_fcvtns>;
2440 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
2699 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2764 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2795 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", AArch64rev16>;
2947 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2954 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
4348 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
4388 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
4984 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4988 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4992 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4996 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
5068 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
5154 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
5158 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
5162 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
