Lines Matching full:aarch64
1 //==- AArch64AsmParser.cpp - Parse AArch64 assembly to MCInst instructions -==//
146 /// AArch64Operand - Instances of this class represent a parsed AArch64 machine
924 AArch64MCRegisterClasses[AArch64::FPR128_loRegClassID].contains(
929 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
933 AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID].contains(
938 AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID].contains(
944 AArch64MCRegisterClasses[AArch64::GPR64spRegClassID].contains(Reg.RegNum);
1181 AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(getReg()));
1184 uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
1193 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].contains(getReg()));
1194 Inst.addOperand(MCOperand::createReg(AArch64::D0 + getReg() - AArch64::Q0));
1200 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].contains(getReg()));
1212 static const unsigned FirstRegs[] = { AArch64::D0,
1213 AArch64::D0_D1,
1214 AArch64::D0_D1_D2,
1215 AArch64::D0_D1_D2_D3 };
1219 MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0));
1225 static const unsigned FirstRegs[] = { AArch64::Q0,
1226 AArch64::Q0_Q1,
1227 AArch64::Q0_Q1_Q2,
1228 AArch64::Q0_Q1_Q2_Q3 };
1232 MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0));
1871 .Case("v0", AArch64::Q0)
1872 .Case("v1", AArch64::Q1)
1873 .Case("v2", AArch64::Q2)
1874 .Case("v3", AArch64::Q3)
1875 .Case("v4", AArch64::Q4)
1876 .Case("v5", AArch64::Q5)
1877 .Case("v6", AArch64::Q6)
1878 .Case("v7", AArch64::Q7)
1879 .Case("v8", AArch64::Q8)
1880 .Case("v9", AArch64::Q9)
1881 .Case("v10", AArch64::Q10)
1882 .Case("v11", AArch64::Q11)
1883 .Case("v12", AArch64::Q12)
1884 .Case("v13", AArch64::Q13)
1885 .Case("v14", AArch64::Q14)
1886 .Case("v15", AArch64::Q15)
1887 .Case("v16", AArch64::Q16)
1888 .Case("v17", AArch64::Q17)
1889 .Case("v18", AArch64::Q18)
1890 .Case("v19", AArch64::Q19)
1891 .Case("v20", AArch64::Q20)
1892 .Case("v21", AArch64::Q21)
1893 .Case("v22", AArch64::Q22)
1894 .Case("v23", AArch64::Q23)
1895 .Case("v24", AArch64::Q24)
1896 .Case("v25", AArch64::Q25)
1897 .Case("v26", AArch64::Q26)
1898 .Case("v27", AArch64::Q27)
1899 .Case("v28", AArch64::Q28)
1900 .Case("v29", AArch64::Q29)
1901 .Case("v30", AArch64::Q30)
1902 .Case("v31", AArch64::Q31)
1988 .Case("fp", AArch64::FP)
1989 .Case("lr", AArch64::LR)
1990 .Case("x31", AArch64::XZR)
1991 .Case("w31", AArch64::WZR)
2543 if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
2590 if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
2597 if (getSTI().getFeatureBits()[AArch64::HasV8_2aOps]) {
3117 if (!RI->getRegClass(AArch64::GPR64spRegClassID).contains(RegNum))
3279 AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
3315 /// ParseInstruction - Parse an AArch64 instruction mnemonic followed by its
3342 // First check for the AArch64-specific .req directive.
3479 case AArch64::LDPSWpre:
3480 case AArch64::LDPWpost:
3481 case AArch64::LDPWpre:
3482 case AArch64::LDPXpost:
3483 case AArch64::LDPXpre: {
3495 case AArch64::LDPDi:
3496 case AArch64::LDPQi:
3497 case AArch64::LDPSi:
3498 case AArch64::LDPSWi:
3499 case AArch64::LDPWi:
3500 case AArch64::LDPXi: {
3507 case AArch64::LDPDpost:
3508 case AArch64::LDPDpre:
3509 case AArch64::LDPQpost:
3510 case AArch64::LDPQpre:
3511 case AArch64::LDPSpost:
3512 case AArch64::LDPSpre:
3513 case AArch64::LDPSWpost: {
3520 case AArch64::STPDpost:
3521 case AArch64::STPDpre:
3522 case AArch64::STPQpost:
3523 case AArch64::STPQpre:
3524 case AArch64::STPSpost:
3525 case AArch64::STPSpre:
3526 case AArch64::STPWpost:
3527 case AArch64::STPWpre:
3528 case AArch64::STPXpost:
3529 case AArch64::STPXpre: {
3541 case AArch64::LDRBBpre:
3542 case AArch64::LDRBpre:
3543 case AArch64::LDRHHpre:
3544 case AArch64::LDRHpre:
3545 case AArch64::LDRSBWpre:
3546 case AArch64::LDRSBXpre:
3547 case AArch64::LDRSHWpre:
3548 case AArch64::LDRSHXpre:
3549 case AArch64::LDRSWpre:
3550 case AArch64::LDRWpre:
3551 case AArch64::LDRXpre:
3552 case AArch64::LDRBBpost:
3553 case AArch64::LDRBpost:
3554 case AArch64::LDRHHpost:
3555 case AArch64::LDRHpost:
3556 case AArch64::LDRSBWpost:
3557 case AArch64::LDRSBXpost:
3558 case AArch64::LDRSHWpost:
3559 case AArch64::LDRSHXpost:
3560 case AArch64::LDRSWpost:
3561 case AArch64::LDRWpost:
3562 case AArch64::LDRXpost: {
3570 case AArch64::STRBBpost:
3571 case AArch64::STRBpost:
3572 case AArch64::STRHHpost:
3573 case AArch64::STRHpost:
3574 case AArch64::STRWpost:
3575 case AArch64::STRXpost:
3576 case AArch64::STRBBpre:
3577 case AArch64::STRBpre:
3578 case AArch64::STRHHpre:
3579 case AArch64::STRHpre:
3580 case AArch64::STRWpre:
3581 case AArch64::STRXpre: {
3595 case AArch64::ADDSWri:
3596 case AArch64::ADDSXri:
3597 case AArch64::ADDWri:
3598 case AArch64::ADDXri:
3599 case AArch64::SUBSWri:
3600 case AArch64::SUBSXri:
3601 case AArch64::SUBWri:
3602 case AArch64::SUBXri: {
3617 Inst.getOpcode() == AArch64::ADDXri)
3629 (Inst.getOpcode() == AArch64::ADDXri ||
3630 Inst.getOpcode() == AArch64::ADDWri))
3653 return Error(Loc, "expected AArch64 condition code");
3794 if (AArch64MCRegisterClasses[AArch64::GPR32allRegClassID].contains(
3829 if (AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
3859 RegWidth == 32 ? AArch64::WZR : AArch64::XZR, false, SMLoc(),
3885 if (AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
3949 if (AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
4004 AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
4020 AArch64MCRegisterClasses[AArch64::GPR64allRegClassID].contains(
4039 !AArch64MCRegisterClasses[AArch64::FPR64RegClassID].contains(
4041 ? AArch64::WZR
4042 : AArch64::XZR;
4298 Inst.setOpcode(AArch64::TLSDESCCALL);
4559 AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
4561 AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
4604 Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube64,
4605 &AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID]);
4607 Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube32,
4608 &AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID]);
