Lines Matching defs:SIInstrInfo
1 //===-- SIInstrInfo.cpp - SI Instruction Information ---------------------===//
16 #include "SIInstrInfo.h"
30 SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
77 bool SIInstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
92 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
204 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
291 bool SIInstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
312 SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
473 int SIInstrInfo::commuteOpcode(const MachineInstr &MI) const {
493 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
539 void SIInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
575 Ctx.emitError("SIInstrInfo::storeRegToStackSlot - Do not know how to"
629 void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
660 Ctx.emitError("SIInstrInfo::loadRegFromStackSlot - Do not know how to"
678 unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
776 void SIInstrInfo::insertWaitStates(MachineBasicBlock::iterator MI,
790 bool SIInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
888 MachineInstr *SIInstrInfo::commuteInstructionImpl(MachineInstr *MI,
974 bool SIInstrInfo::findCommutedOpIndices(MachineInstr *MI,
988 // SIInstrInfo::commuteInstruction();
998 // SIInstrInfo::commuteInstruction() does support commuting the immediate
1014 MachineInstr *SIInstrInfo::buildMovInstr(MachineBasicBlock *MBB,
1022 bool SIInstrInfo::isMov(unsigned Opcode) const {
1047 bool SIInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
1180 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr *MIa,
1200 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,
1251 MachineInstr *SIInstrInfo::convertToThreeAddress(MachineFunction::iterator &MBB,
1283 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
1322 bool SIInstrInfo::isInlineConstant(const MachineOperand &MO,
1338 bool SIInstrInfo::isLiteralConstant(const MachineOperand &MO,
1358 bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo,
1377 bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const {
1385 bool SIInstrInfo::hasModifiers(unsigned Opcode) const {
1393 bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
1399 bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
1451 bool SIInstrInfo::verifyInstruction(const MachineInstr *MI,
1583 unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
1646 bool SIInstrInfo::isSALUOpSupportedOnVALU(const MachineInstr &MI) const {
1650 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
1667 bool SIInstrInfo::canReadVGPR(const MachineInstr &MI, unsigned OpNo) const {
1679 void SIInstrInfo::legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const {
1706 unsigned SIInstrInfo::buildExtractSubReg(MachineBasicBlock::iterator MI,
1738 MachineOperand SIInstrInfo::buildExtractSubRegOrImm(
1761 void SIInstrInfo::swapOperands(MachineBasicBlock::iterator Inst) const {
1768 bool SIInstrInfo::isLegalRegOperand(const MachineRegisterInfo &MRI,
1792 bool SIInstrInfo::isLegalVSrcOperand(const MachineRegisterInfo &MRI,
1803 bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
1845 void SIInstrInfo::legalizeOperandsVOP2(MachineRegisterInfo &MRI,
1924 void SIInstrInfo::legalizeOperandsVOP3(
1963 void SIInstrInfo::legalizeOperands(MachineInstr *MI) const {
2234 void SIInstrInfo::splitSMRD(MachineInstr *MI,
2337 void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI,
2445 void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const {
2613 unsigned SIInstrInfo::calculateIndirectAddress(unsigned RegIndex,
2619 const TargetRegisterClass *SIInstrInfo::getIndirectAddrRegClass() const {
2623 void SIInstrInfo::lowerScalarAbs(SmallVectorImpl<MachineInstr *> &Worklist,
2647 void SIInstrInfo::splitScalar64BitUnaryOp(
2701 void SIInstrInfo::splitScalar64BitBinaryOp(
2769 void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
2810 void SIInstrInfo::splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
2873 void SIInstrInfo::addUsersToMoveToVALUWorklist(
2886 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
2911 unsigned SIInstrInfo::findUsedSGPR(const MachineInstr *MI,
2980 MachineInstrBuilder SIInstrInfo::buildIndirectWrite(
2998 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
3016 void SIInstrInfo::reserveIndirectRegisters(BitVector &Reserved,
3044 MachineOperand *SIInstrInfo::getNamedOperand(MachineInstr &MI,
3053 uint64_t SIInstrInfo::getDefaultRsrcDataFormat() const {
3066 uint64_t SIInstrInfo::getScratchRsrcWords23() const {
