Lines Matching full:issigned
3921 /*isSigned*/ false, SDLoc(Op)).first;
3973 /*isSigned*/ false, SDLoc(Op)).first;
6151 /// element has been zero/sign-extended, depending on the isSigned parameter,
6154 bool isSigned) {
6170 if (isSigned) {
6189 if (isSigned) {
10014 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
10015 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
10072 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
10075 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
10079 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
11526 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
11531 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
11532 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
11533 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
11534 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
11544 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
11553 Entry.isSExt = isSigned;
11554 Entry.isZExt = !isSigned;
11566 bool isSigned = (Opcode == ISD::SDIVREM);
11586 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
11616 bool isSigned = N->getOpcode() == ISD::SREM;
11624 .setSExtResult(isSigned).setZExtResult(!isSigned).setDebugLoc(SDLoc(N));
11667 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
11680 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
