Home | History | Annotate | Download | only in ARM

Lines Matching refs:ArgValue

2951   SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2969 std::swap (ArgValue, ArgValue2);
2970 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3080 SDValue ArgValue;
3155 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3156 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3157 ArgValue, ArgValue1,
3159 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3160 ArgValue, ArgValue2,
3163 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3182 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3192 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3195 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3197 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3200 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3202 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3206 InVals.push_back(ArgValue);