Lines Matching full:simm
3127 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3128 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3129 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3134 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3135 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3136 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3145 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3146 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3147 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3155 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3156 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3158 (i32 ImmTy:$SIMM))))]>;
3167 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3168 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3170 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
3175 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3176 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3178 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3188 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
3189 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3190 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3195 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3196 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3197 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3206 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3207 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3208 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3213 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3214 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3215 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
4866 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4868 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4870 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4871 let Inst{9} = SIMM{9};
4875 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4877 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4879 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4880 let Inst{10-9} = SIMM{10-9};
4884 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4886 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4888 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4889 let Inst{9} = SIMM{9};
4893 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4895 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4897 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4898 let Inst{10-9} = SIMM{10-9};
4917 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4919 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4921 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4922 let Inst{9} = SIMM{9};
4926 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4928 "vbic", "i32", "$Vd, $SIMM
4930 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4931 let Inst{10-9} = SIMM{10-9};
4935 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4937 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4939 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4940 let Inst{9} = SIMM{9};
4944 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4946 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4948 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4949 let Inst{10-9} = SIMM{10-9};
4969 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4970 "vmvn", "i16", "$Vd, $SIMM", "",
4971 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4972 let Inst{9} = SIMM{9};
4976 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4977 "vmvn", "i16", "$Vd, $SIMM", "",
4978 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4979 let Inst{9} = SIMM{9};
4983 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4984 "vmvn", "i32", "$Vd, $SIMM", "",
4985 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4986 let Inst{11-8} = SIMM{11-8};
4990 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4991 "vmvn", "i32", "$Vd, $SIMM", "",
4992 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4993 let Inst{11-8} = SIMM{11-8};
5694 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5695 "vmov", "i8", "$Vd, $SIMM", "",
5696 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
5698 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5699 "vmov", "i8", "$Vd, $SIMM", "",
5700 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5703 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5704 "vmov", "i16", "$Vd, $SIMM", "",
5705 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
5706 let Inst{9} = SIMM{9};
5710 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5711 "vmov", "i16", "$Vd, $SIMM", "",
5712 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5713 let Inst{9} = SIMM{9};
5717 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5718 "vmov", "i32", "$Vd, $SIMM", "",
5719 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
5720 let Inst{11-8} = SIMM{11-8};
5724 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5725 "vmov", "i32", "$Vd, $SIMM", "",
5726 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5727 let Inst{11-8} = SIMM{11-8};
5731 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5732 "vmov", "i64", "$Vd, $SIMM", "",
5733 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
5735 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5736 "vmov", "i64", "$Vd, $SIMM", "",
5737 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5740 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5741 "vmov", "f32", "$Vd, $SIMM", "",
5742 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
5744 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5745 "vmov", "f32", "$Vd, $SIMM", "",
5746 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
