Lines Matching full:b00
602 let Inst{7-6} = 0b00; // imm2
603 let Inst{5-4} = 0b00; // type
686 let Inst{7-6} = 0b00; // imm2
687 let Inst{5-4} = 0b00; // type
807 let Inst{7-6} = 0b00; // imm2
808 let Inst{5-4} = 0b00; // type
849 let Inst{7-6} = 0b00; // imm2
850 let Inst{5-4} = 0b00; // type
947 let Inst{7-6} = 0b00; // imm2
948 let Inst{5-4} = 0b00; // type
999 let Inst{26-25} = 0b00;
1019 let Inst{26-25} = 0b00;
1044 let Inst{26-25} = 0b00;
1269 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1275 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1343 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1348 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1363 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1369 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1394 let Inst{26-25} = 0b00;
1409 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
1411 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
1435 def t2LDAB : T2Ildacq<0b1101, 0b00, (outs rGPR:$Rt),
1443 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si,
1469 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
1496 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb),
1537 let Inst{26-25} = 0b00;
1553 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>;
1606 def t2STLB : T2Istrrel<0b00, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
1717 let Inst{26-25} = 0b00;
1732 let Inst{26-25} = 0b00;
1747 let Inst{26-25} = 0b00;
1762 let Inst{26-25} = 0b00;
1786 let Inst{26-25} = 0b00;
1804 let Inst{26-25} = 0b00;
1822 let Inst{26-25} = 0b00;
1840 let Inst{26-25} = 0b00;
2267 let Inst{7-6} = 0b00; // imm2 = '00'
2268 let Inst{5-4} = 0b00;
2290 let Inst{7-6} = 0b00; // imm2 = '00'
2291 let Inst{5-4} = 0b00;
2301 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31,
2500 let Inst{7-6} = 0b00; // imm2
2501 let Inst{5-4} = 0b00; // type
2690 let Inst{7-6} = 0b00;
2691 let Inst{5-4} = 0b00;
2703 let Inst{7-6} = 0b00;
2716 let Inst{7-6} = 0b00;
2729 let Inst{7-6} = 0b00;
2741 let Inst{7-6} = 0b00;
2742 let Inst{5-4} = 0b00;
2753 let Inst{7-6} = 0b00;
2770 let Inst{7-6} = 0b00;
2771 let Inst{5-4} = 0b00;
2783 let Inst{7-6} = 0b00;
2796 let Inst{7-6} = 0b00;
2809 let Inst{7-6} = 0b00;
2821 let Inst{7-6} = 0b00;
2822 let Inst{5-4} = 0b00;
2833 let Inst{7-6} = 0b00;
2961 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
2970 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3072 def t2CRC32B : T2I_crc32<0, 0b00, "b", int_arm_crc32b>;
3073 def t2CRC32CB : T2I_crc32<1, 0b00, "cb", int_arm_crc32cb>;
3119 let Inst{7-6} = 0b00; // imm2
3120 let Inst{5-4} = 0b00; // type
3779 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary,
3781 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary,
4111 let Inst{9-8} = 0b00;
