Lines Matching defs:MBB
130 void moveLiveRegsBefore(const MachineBasicBlock &MBB,
133 void UpdateBaseRegUses(MachineBasicBlock &MBB,
137 MachineInstr *CreateLoadStoreMulti(MachineBasicBlock &MBB,
141 MachineInstr *CreateLoadStoreDouble(MachineBasicBlock &MBB,
147 bool FixInvalidRegPairOp(MachineBasicBlock &MBB,
152 bool LoadStoreMultipleOpti(MachineBasicBlock &MBB);
153 bool MergeReturnIntoLDM(MachineBasicBlock &MBB);
154 bool CombineMovBx(MachineBasicBlock &MBB);
440 ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB,
448 for (; MBBI != MBB.end(); ++MBBI) {
511 AddDefaultT1CC(BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base), true)
522 if (MBB.succ_size() > 0) {
527 if (MBBI != MBB.end()) --MBBI;
529 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base), true)
550 void ARMLoadStoreOpt::moveLiveRegsBefore(const MachineBasicBlock &MBB,
555 LiveRegs.addLiveOuts(&MBB, true);
556 LiveRegPos = MBB.end();
577 MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti(MachineBasicBlock &MBB,
587 (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) ==
640 moveLiveRegsBefore(MBB, InsertBefore);
689 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVSr), NewBase)
692 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase)
702 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
707 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase), true)
711 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
748 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
757 UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);
761 MIB = BuildMI(MBB, InsertBefore, DL, TII->get(Opcode));
773 MachineInstr *ARMLoadStoreOpt::CreateLoadStoreDouble(MachineBasicBlock &MBB,
782 MachineInstrBuilder MIB = BuildMI(MBB, InsertBefore, DL,
838 MachineBasicBlock &MBB = *LatestMI->getParent();
847 Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,
850 Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,
859 if (EarliestI == MBB.begin()) {
867 MBB.erase(MI);
871 EarliestI = MBB.begin();
1119 MachineBasicBlock &MBB = *MBBI->getParent();
1120 MachineBasicBlock::iterator BeginMBBI = MBB.begin();
1121 MachineBasicBlock::iterator EndMBBI = MBB.end();
1139 MachineBasicBlock &MBB = *MBBI->getParent();
1140 MachineBasicBlock::iterator EndMBBI = MBB.end();
1183 MachineBasicBlock &MBB = *MI->getParent();
1199 MBB.erase(MergeInstr);
1202 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1214 MBB.erase(MBBI);
1296 MachineBasicBlock &MBB = *MI->getParent();
1315 MBB.erase(MergeInstr);
1326 BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1336 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1341 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1347 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1359 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1364 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1369 MBB.erase(MBBI);
1393 MachineBasicBlock &MBB = *MI.getParent();
1407 MBB.erase(MergeInstr);
1410 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
1430 MBB.erase(MBBI);
1489 static void InsertLDR_STR(MachineBasicBlock &MBB,
1499 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1505 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1513 bool ARMLoadStoreOpt::FixInvalidRegPairOp(MachineBasicBlock &MBB,
1561 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1568 BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(NewOpc))
1594 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2,
1598 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
1613 InsertLDR_STR(MBB, MBBI, OffImm, isLd, dl, NewOpc,
1617 InsertLDR_STR(MBB, MBBI, OffImm+4, isLd, dl, NewOpc2,
1628 MBBI = MBB.erase(MBBI);
1634 bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
1644 for (MachineBasicBlock::iterator I = MBB.end(), MBBI; I != MBB.begin();
1648 if (FixInvalidRegPairOp(MBB, MBBI))
1794 bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) {
1797 if (MBB.empty()) return false;
1799 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
1800 if (MBBI != MBB.begin() &&
1806 while (PrevI->isDebugValue() && PrevI != MBB.begin())
1821 PrevMI->copyImplicitOps(*MBB.getParent(), &*MBBI);
1822 MBB.erase(MBBI);
1829 bool ARMLoadStoreOpt::CombineMovBx(MachineBasicBlock &MBB) {
1830 MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
1831 if (MBBI == MBB.begin() || MBBI == MBB.end() ||
1842 AddDefaultPred(BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(ARM::tBX))
1845 MBB.erase(MBBI);
1846 MBB.erase(Prev);
1868 MachineBasicBlock &MBB = *MFI;
1869 Modified |= LoadStoreMultipleOpti(MBB);
1871 Modified |= MergeReturnIntoLDM(MBB);
1873 Modified |= CombineMovBx(MBB);
1916 bool RescheduleOps(MachineBasicBlock *MBB,
1920 bool RescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
2081 bool ARMPreAllocLoadStoreOpt::RescheduleOps(MachineBasicBlock *MBB,
2161 while (InsertPos != MBB->end()
2189 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
2203 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
2217 MBB->erase(Op0);
2218 MBB->erase(Op1);
2229 MBB->splice(InsertPos, MBB, Op);
2243 ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
2253 MachineBasicBlock::iterator MBBI = MBB->begin();
2254 MachineBasicBlock::iterator E = MBB->end();
2326 RetVal |= RescheduleOps(MBB, Lds, Base, true, MI2LocMap);
2334 RetVal |= RescheduleOps(MBB, Sts, Base, false, MI2LocMap);
