Lines Matching defs:Encoded
267 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
272 /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
284 // In instruction code this value always encoded as lowest 12 bits,
315 // In instruction code this value always encoded as lowest 12 bits,
325 // Immediate is already in its encoded format
329 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
334 unsigned Encoded = ARM_AM::getT2SOImmVal(SoImm);
335 assert(Encoded != ~0U && "Not a Thumb2 so_imm value?");
336 return Encoded;
352 /// getSORegOpValue - Return an encoded so_reg shifted register value.
454 /// NEONThumb2DataIPostEncoder - Post-process encoded NEON data-processing
474 /// NEONThumb2LoadStorePostEncoder - Post-process encoded NEON load/store
488 /// NEONThumb2DupPostEncoder - Post-process encoded NEON vdup
502 /// Post-process encoded NEON v8 instructions, and rewrite them to Thumb2 form
514 /// VFPThumb2PostEncoder - Post-process encoded VFP instructions and rewrite
536 // Q registers are encoded as 2x their register number.
575 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
922 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
935 // FIXME: The immediate operand should have already been encoded like this
947 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
955 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
988 // FIXME: The immediate operand should have already been encoded like this
995 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1087 // While "lsr #32" and "asr #32" exist, they are encoded with a 0 in the shift
1288 // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
1398 // Encoded as [Rn, Rm, imm].
1672 // Pseudo instructions don't get encoded.
