Lines Matching refs:ISD
107 ISD::ArgFlagsTy ArgFlags, CCState &State);
112 ISD::ArgFlagsTy ArgFlags, CCState &State);
117 ISD::ArgFlagsTy ArgFlags, CCState &State);
122 ISD::ArgFlagsTy ArgFlags, CCState &State);
127 ISD::ArgFlagsTy ArgFlags, CCState &State);
132 ISD::ArgFlagsTy ArgFlags, CCState &State);
137 ISD::ArgFlagsTy ArgFlags, CCState &State);
142 ISD::ArgFlagsTy ArgFlags, CCState &State);
147 ISD::ArgFlagsTy ArgFlags, CCState &State) {
221 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) {
274 ISD::ArgFlagsTy ArgFlags, CCState &State) {
292 ISD::ArgFlagsTy ArgFlags, CCState &State) {
317 ISD::ArgFlagsTy ArgFlags, CCState &State) {
386 ISD::ArgFlagsTy ArgFlags, CCState &State) {
445 ISD::ArgFlagsTy ArgFlags, CCState &State) {
461 ISD::ArgFlagsTy ArgFlags, CCState &State) {
476 ISD::ArgFlagsTy ArgFlags, CCState &State) {
510 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
511 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(),
514 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
515 AddPromotedToType(ISD::STORE, VT.getSimpleVT(),
533 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
553 // LowerReturn - Lower ISD::RET. If a struct is larger than 8 bytes and is
559 const SmallVectorImpl<ISD::OutputArg> &Outs,
570 // Analyze return values of ISD::RET
606 /// LowerCallResult - Lower the result values of an ISD::CALL into the
610 /// ISD::CALL.
615 SmallVectorImpl<ISD::InputArg> &Ins,
648 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
650 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
722 ISD::ArgFlagsTy Flags = Outs[i].Flags;
736 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
739 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
742 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
750 MemAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, MemAddr);
789 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
877 if (Ptr->getOpcode() != ISD::ADD)
893 isInc = (Ptr->getOpcode() == ISD::ADD);
909 ISD::MemIndexedMode &AM,
918 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
935 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
949 case ISD::INLINEASM: {
1029 SmallVectorImpl<ISD::InputArg> &Ins,
1058 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1155 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1195 if (N.getOpcode() == ISD::TRUNCATE &&
1196 N.getOperand(0).getOpcode() == ISD::AssertSext)
1199 if (N.getOpcode() == ISD::LOAD)
1212 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, PopOut);
1221 ISD::CondCode CC = cast<CondCodeSDNode>(Cmp)->get();
1228 assert(ISD::isSignedIntSetCC(CC) || ISD::isUnsignedIntSetCC(CC));
1229 unsigned ExtOpc = ISD::isSignedIntSetCC(CC) ? ISD::SIGN_EXTEND
1230 : ISD::ZERO_EXTEND;
1233 SDValue SC = DAG.getNode(ISD::SETCC, dl, MVT::v2i1, LX, RX, Cmp);
1244 if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
1249 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1250 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1251 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1255 LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
1256 RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
1257 return DAG.getNode(ISD::SETCC, dl, Op.getValueType(),
1272 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1);
1273 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2);
1274 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2);
1275 SDValue TR = DAG.getNode(ISD::TRUNCATE, DL, MVT::v2i16, SL);
1292 ISD::LoadExtType Ext = LoadNode->getExtensionType();
1296 if(Ext == ISD::NON_EXTLOAD)
1297 Ext = ISD::ZEXTLOAD;
1311 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1320 SDValue Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[1], ShiftAmount);
1321 SDValue Tmp2 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[0]);
1324 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1333 Ptr = DAG.getNode(ISD::ADD, DL, Base.getValueType(), Base, Increment);
1341 Tmp1 = DAG.getNode(ISD::SHL, DL, MVT::i32, Loads[3], ShiftAmount);
1342 SDValue Tmp4 = DAG.getNode(ISD::OR, DL, MVT::i32, Tmp1, Loads[2]);
1346 LoadChain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
1359 Result = DAG.getNode(ISD::BITCAST, DL, VT, Result);
1417 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
1601 setOperationAction(ISD::ConstantFP, MVT::f32, Legal); // Default: expand
1602 setOperationAction(ISD::ConstantFP, MVT::f64, Legal); // Default: expand
1604 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
1605 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
1606 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
1607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
1608 setOperationAction(ISD::INLINEASM, MVT::Other, Custom);
1609 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
1610 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
1611 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
1614 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
1615 setOperationAction(ISD::GlobalAddress, MVT::i8, Custom);
1616 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
1619 setOperationAction(ISD::SETCC, MVT::i8, Custom);
1620 setOperationAction(ISD::SETCC, MVT::i16, Custom);
1623 setOperationAction(ISD::VASTART, MVT::Other, Custom);
1624 setOperationAction(ISD::VAEND, MVT::Other, Expand);
1625 setOperationAction(ISD::VAARG, MVT::Other, Expand);
1627 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
1628 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
1629 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
1635 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1642 setOperationAction(ISD::ADDE, MVT::i8, Expand);
1643 setOperationAction(ISD::ADDE, MVT::i16, Expand);
1644 setOperationAction(ISD::ADDE, MVT::i32, Expand);
1645 setOperationAction(ISD::ADDE, MVT::i64, Expand);
1646 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1647 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1648 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1649 setOperationAction(ISD::SUBE, MVT::i64, Expand);
1650 setOperationAction(ISD::ADDC, MVT::i8, Expand);
1651 setOperationAction(ISD::ADDC, MVT::i16, Expand);
1652 setOperationAction(ISD::ADDC, MVT::i32, Expand);
1653 setOperationAction(ISD::ADDC, MVT::i64, Expand);
1654 setOperationAction(ISD::SUBC, MVT::i8, Expand);
1655 setOperationAction(ISD::SUBC, MVT::i16, Expand);
1656 setOperationAction(ISD::SUBC, MVT::i32, Expand);
1657 setOperationAction(ISD::SUBC, MVT::i64, Expand);
1661 setOperationAction(ISD::UADDO, VT, Expand);
1662 ISD::SADDO, VT, Expand);
1663 setOperationAction(ISD::USUBO, VT, Expand);
1664 setOperationAction(ISD::SSUBO, VT, Expand);
1667 setOperationAction(ISD::CTLZ, MVT::i8, Promote);
1668 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
1669 setOperationAction(ISD::CTTZ, MVT::i8, Promote);
1670 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
1671 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i8, Promote);
1672 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
1673 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i8, Promote);
1674 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
1678 setOperationAction(ISD::CTPOP, MVT::i8, Promote);
1679 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
1680 setOperationAction(ISD::CTPOP, MVT::i32, Promote);
1681 setOperationAction(ISD::CTPOP, MVT::i64, Custom);
1686 setOperationAction(ISD::MUL, MVT::i64, Expand);
1687 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1690 { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1691 ISD::SDIVREM, ISD::UDIVREM, ISD::ROTL, ISD::ROTR,
1692 ISD::BSWAP, ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS,
1693 ISD::SMUL_LOHI, ISD::UMUL_LOHI }) {
1699 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1700 ISD::FPOW, ISD::FCOPYSIGN}) {
1707 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1708 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i32, Expand);
1709 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i32, Expand);
1715 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1719 setOperationAction(ISD::BR_CC, VT, Expand);
1720 setOperationAction(ISD::SELECT_CC, VT, Expand);
1723 setOperationAction(ISD::BR_CC, VT, Expand);
1724 setOperationAction(ISD::SELECT_CC, VT, Expand);
1726 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
1739 setOperationAction(ISD::LOAD, MVT::v4i16, Custom);
1740 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
1741 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64);
1742 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::i64);
1748 ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
1749 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC,
1750 ISD::SUBC, ISD::SADDO, ISD::UADDO, ISD::SSUBO, ISD::USUBO,
1751 ISD::SMUL_LOHI, ISD::UMUL_LOHI,
1753 ISD::AND, ISD::OR, ISD::XOR, ISD::ROTL, ISD::ROTR,
1754 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::CTLZ_ZERO_UNDEF,
1755 ISD::CTTZ_ZERO_UNDEF,
1757 ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FMA, ISD::FDIV,
1758 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
1759 ISD::FCOS, ISD::FPOWI, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
1760 ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
1761 ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1762 ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS,
1764 ISD::SELECT, ISD::ConstantPool,
1766 ISD::BUILD_VECTOR, ISD::SCALAR_TO_VECTOR,
1767 ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT,
1768 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR,
1769 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE
1778 setLoadExtAction(ISD::EXTLOAD, TargetVT, VT, Expand);
1782 setOperationAction(ISD::SRA, VT, Custom);
1783 setOperationAction(ISD::SHL, VT, Custom);
1784 setOperationAction(ISD::SRL, VT, Custom);
1791 setOperationAction(ISD::BUILD_VECTOR, NativeVT, Custom);
1792 setOperationAction(ISD::EXTRACT_VECTOR_ELT, NativeVT, Custom);
1793 setOperationAction(ISD::INSERT_VECTOR_ELT, NativeVT, Custom);
1794 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom);
1795 setOperationAction(ISD::INSERT_SUBVECTOR, NativeVT, Custom);
1796 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom);
1798 setOperationAction(ISD::ADD, NativeVT, Legal);
1799 setOperationAction(ISD::SUB, NativeVT, Legal);
1800 setOperationAction(ISD::MUL, NativeVT, Legal);
1801 setOperationAction(ISD::AND, NativeVT, Legal);
1802 setOperationAction(ISD::OR, NativeVT, Legal);
1803 setOperationAction(ISD::XOR, NativeVT, Legal);
1806 setOperationAction(ISD::SETCC, MVT::v2i16, Custom);
1807 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom);
1808 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom);
1809 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom);
1812 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom);
1813 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom);
1814 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom);
1815 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom);
1817 setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom);
1818 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom);
1819 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom);
1820 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom);
1828 setOperationAction(ISD::FMA, MVT::f64, Expand);
1829 setOperationAction(ISD::FADD, MVT::f64, Expand);
1830 setOperationAction(ISD::FSUB, MVT::f64, Expand);
1831 setOperationAction(ISD::FMUL, MVT::f64, Expand);
1833 setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
1834 setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
1835 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
1836 setOperationAction(ISD::FP_TO_SINT, MVT::i1, Promote);
1837 setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote);
1838 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
1839 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
1840 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote);
1841 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
1842 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
1843 setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote);
1844 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
1847 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
1848 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Expand);
1849 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
1850 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
1851 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Expand);
1852 setOperationAction(ISD::FP_TO_SINT, MVT::f32, Expand);
1853 setOperationAction(ISD::FP_EXTEND, MVT::f32, Expand);
1854 setOperationAction(ISD::FP_ROUND, MVT::f64, Expand);
1855 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand);
1857 setOperationAction(ISD::CTPOP, MVT::i8, Expand);
1858 setOperationAction(ISD::CTPOP, MVT::i16, Expand);
1859 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
1860 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
1864 {ISD::FADD, ISD::FSUB, ISD::FMUL, ISD::FABS, ISD::FNEG, ISD::FMA}) {
1869 for (ISD::CondCode FPExpCCV4 :
1870 {ISD::SETOEQ, ISD::SETOGT, ISD::SETOLT, ISD::SETOGE, ISD::SETOLE,
1871 ISD::SETUO, ISD::SETO}) {
1880 setIndexedLoadAction(ISD::POST_INC, LSXTy, Legal);
1881 setIndexedStoreAction(ISD::POST_INC, LSXTy, Legal);
1886 setIndexedLoadAction(ISD::POST_INC, VT, Legal);
1887 setIndexedStoreAction(ISD::POST_INC, VT, Legal);
2098 if (V2.getOpcode() == ISD::UNDEF)
2106 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR)
2112 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
2116 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
2173 case ISD::SRA:
2176 case ISD::SHL:
2179 case ISD::SRL:
2187 case ISD::SRA:
2190 case ISD::SHL:
2193 case ISD::SRL:
2203 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
2238 if (V0.getOpcode() == ISD::UNDEF)
2240 if (V1.getOpcode() == ISD::UNDEF)
2260 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
2288 if (Operand.getOpcode() == ISD::UNDEF)
2311 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2330 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, Width);
2331 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2341 return DAG.getNode(ISD::BITCAST, dl, VT, ConstVal);
2368 SDValue B0 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec0);
2369 SDValue B1 = DAG.getNode(ISD::BITCAST, dl, OpTy, Vec1);
2371 return DAG.getNode(ISD::BITCAST, dl, VT, VC);
2382 SDValue S = DAG.getNode(ISD::SHL, dl, MVT::i64, W, C32);
2394 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i64, Idx, W);
2395 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, S, Offset);
2402 return DAG.getNode(ISD::BITCAST, dl, VT, V);
2416 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT ?
2456 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2460 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2462 SDValue Shifted = DAG.getNode(ISD
2464 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2476 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2491 SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
2504 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2508 SDValue Offset = DAG.getNode(ISD::MUL, dl, MVT::i32, Idx,
2510 SDValue Shifted = DAG.getNode(ISD::SHL, dl, MVT::i64, Width,
2512 SDValue Combined = DAG.getNode(ISD::OR, dl, MVT::i64, Shifted, Offset);
2528 return DAG.getNode(ISD::BITCAST, dl, VT, N);
2560 DAG.getNode(ISD::ADD, dl, PtrVT, DAG.getRegister(Hexagon::R30, PtrVT),
2583 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2584 case ISD::INSERT_SUBVECTOR: return LowerINSERT_VECTOR(Op, DAG);
2585 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR(Op, DAG);
2586 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_VECTOR(Op, DAG);
2587 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR(Op, DAG);
2588 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2589 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2590 case ISD::SRA:
2591 case ISD::SHL:
2592 case ISD::SRL: return LowerVECTOR_SHIFT(Op, DAG);
2593 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2594 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2595 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
2597 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
2598 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2599 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
2600 case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG);
2601 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2602 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2603 case ISD::VASTART: return LowerVASTART(Op, DAG);
2605 case ISD::LOAD: return LowerLOAD(Op, DAG);
2606 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2607 case ISD::SETCC: return LowerSETCC(Op, DAG);
2608 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
2609 case ISD::CTPOP: return LowerCTPOP(Op, DAG);
2610 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2611 case ISD::INLINEASM: return LowerINLINEASM(Op, DAG);
2764 const SmallVectorImpl<ISD::OutputArg> &Outs,
2766 const SmallVectorImpl<ISD::InputArg> &Ins,
2812 case ISD::SIGN_EXTEND_INREG:
