Lines Matching full:const
33 const HexagonRegisterInfo RI;
46 unsigned isLoadFromStackSlot(const MachineInstr *MI,
47 int &FrameIndex) const override;
54 unsigned isStoreToStackSlot(const MachineInstr *MI,
55 int &FrameIndex) const override;
85 bool AllowModify) const override;
90 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
104 DebugLoc DL) const override;
113 BranchProbability Probability) const override;
125 BranchProbability Probability) const override;
134 BranchProbability Probability) const override;
147 bool KillSrc) const override;
156 const TargetRegisterClass *RC,
157 const TargetRegisterInfo *TRI) const override;
165 const TargetRegisterClass *RC,
166 const TargetRegisterInfo *TRI) const override;
174 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
179 const override;
183 MachineBasicBlock::iterator MI) const override;
186 bool isPredicated(const MachineInstr *MI) const override;
191 ArrayRef<MachineOperand> Cond) const override;
196 ArrayRef<MachineOperand> Pred2) const override;
202 std::vector<MachineOperand> &Pred) const override;
207 bool isPredicable(MachineInstr *MI) const override;
211 bool isSchedulingBoundary(const MachineInstr *MI,
212 const MachineBasicBlock *MBB,
213 const MachineFunction &MF) const override;
217 unsigned getInlineAsmLength(const char *Str,
218 const MCAsmInfo &MAI) const override;
223 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
224 const ScheduleDAG *DAG) const override;
230 bool analyzeCompare(const MachineInstr *MI,
232 int &Mask, int &Value) const override;
237 unsigned getInstrLatency(const InstrItineraryData *ItinData,
238 const MachineInstr *MI,
239 unsigned *PredCost = 0) const override;
243 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
251 const override;
257 const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
259 unsigned createVR(MachineFunction* MF, MVT VT) const;
261 bool isAbsoluteSet(const MachineInstr* MI) const;
262 bool isAccumulator(const MachineInstr *MI) const;
263 bool isComplex(const MachineInstr *MI) const;
264 bool isCompoundBranchInstr(const MachineInstr *MI) const;
265 bool isCondInst(const MachineInstr *MI) const;
266 bool isConditionalALU32 (const MachineInstr* MI) const;
267 bool isConditionalLoad(const MachineInstr* MI) const;
268 bool isConditionalStore(const MachineInstr* MI) const;
269 bool isConditionalTransfer(const MachineInstr* MI) const;
270 bool isConstExtended(const MachineInstr *MI) const;
271 bool isDeallocRet(const MachineInstr *MI) const;
272 bool isDependent(const MachineInstr *ProdMI,
273 const MachineInstr *ConsMI) const;
274 bool isDotCurInst(const MachineInstr* MI) const;
275 bool isDotNewInst(const MachineInstr* MI) const;
276 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
277 bool isEarlySourceInstr(const MachineInstr *MI) const;
278 bool isEndLoopN(unsigned Opcode) const;
279 bool isExpr(unsigned OpType) const;
280 bool isExtendable(const MachineInstr* MI) const;
281 bool isExtended(const MachineInstr* MI) const;
282 bool isFloat(const MachineInstr *MI) const;
283 bool isHVXMemWithAIndirect(const MachineInstr *I,
284 const MachineInstr *J) const;
285 bool isIndirectCall(const MachineInstr *MI) const;
286 bool isIndirectL4Return(const MachineInstr *MI) const;
287 bool isJumpR(const MachineInstr *MI) const;
288 bool isJumpWithinBranchRange(const MachineInstr *MI, unsigned offset) const;
289 bool isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI,
290 const MachineInstr *ESMI) const;
291 bool isLateResultInstr(const MachineInstr *MI) const;
292 bool isLateSourceInstr(const MachineInstr *MI) const;
293 bool isLoopN(const MachineInstr *MI) const;
294 bool isMemOp(const MachineInstr *MI) const;
295 bool isNewValue(const MachineInstr* MI) const;
296 bool isNewValue(unsigned Opcode) const;
297 bool isNewValueInst(const MachineInstr* MI) const;
298 bool isNewValueJump(const MachineInstr* MI) const;
299 bool isNewValueJump(unsigned Opcode) const;
300 bool isNewValueStore(const MachineInstr* MI) const;
301 bool isNewValueStore(unsigned Opcode) const;
302 bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const;
303 bool isPostIncrement(const MachineInstr* MI) const;
304 bool isPredicatedNew(const MachineInstr *MI) const;
305 bool isPredicatedNew(unsigned Opcode) const;
306 bool isPredicatedTrue(const MachineInstr *MI) const;
307 bool isPredicatedTrue(unsigned Opcode) const;
308 bool isPredicated(unsigned Opcode) const;
309 bool isPredicateLate(unsigned Opcode) const;
310 bool isPredictedTaken(unsigned Opcode) const;
311 bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const;
312 bool isSolo(const MachineInstr* MI) const;
313 bool isSpillPredRegOp(const MachineInstr *MI) const;
314 bool isTC1(const MachineInstr *MI) const;
315 bool isTC2(const MachineInstr *MI) const;
316 bool isTC2Early(const MachineInstr *MI) const;
317 bool isTC4x(const MachineInstr *MI) const;
318 bool isV60VectorInstruction(const MachineInstr *MI) const;
319 bool isValidAutoIncImm(const EVT VT, const int Offset) const;
320 bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
321 bool isVecAcc(const MachineInstr *MI) const;
322 bool isVecALU(const MachineInstr *MI) const;
323 bool isVecUsableNextPacket(const MachineInstr *ProdMI,
324 const MachineInstr *ConsMI) const;
327 bool canExecuteInBundle(const MachineInstr *First,
328 const MachineInstr *Second) const;
329 bool hasEHLabel(const MachineBasicBlock *B) const;
330 bool hasNonExtEquivalent(const MachineInstr *MI) const;
331 const MachineInstr *MI) const;
332 bool hasUncondBranch(const MachineBasicBlock *B) const;
333 bool mayBeCurLoad(const MachineInstr* MI) const;
334 bool mayBeNewStore(const MachineInstr* MI) const;
335 bool producesStall(const MachineInstr *ProdMI,
336 const MachineInstr *ConsMI) const;
337 bool producesStall(const MachineInstr *MI,
338 MachineBasicBlock::const_instr_iterator MII) const;
339 bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const;
340 bool PredOpcodeHasJMP_c(unsigned Opcode) const;
341 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const;
344 unsigned getAddrMode(const MachineInstr* MI) const;
345 unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset,
346 unsigned &AccessSize) const;
347 bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos,
348 unsigned &OffsetPos) const;
349 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const;
350 unsigned getCExtOpNum(const MachineInstr *MI) const;
352 getCompoundCandidateGroup(const MachineInstr *MI) const;
353 unsigned getCompoundOpcode(const MachineInstr *GA,
354 const MachineInstr *GB) const;
355 int getCondOpcode(int Opc, bool sense) const;
356 int getDotCurOp(const MachineInstr* MI) const;
357 int getDotNewOp(const MachineInstr* MI) const;
358 int getDotNewPredJumpOp(const MachineInstr *MI,
359 const MachineBranchProbabilityInfo *MBPI) const;
360 int getDotNewPredOp(const MachineInstr *MI,
361 const MachineBranchProbabilityInfo *MBPI) const;
362 int getDotOldOp(const int opc) const;
363 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI)
364 const;
365 short getEquivalentHWInstr(const MachineInstr *MI) const;
366 MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const;
367 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData,
368 const MachineInstr *MI) const;
369 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const;
370 unsigned getInvertedPredicatedOpcode(const int Opc) const;
371 int getMaxValue(const MachineInstr *MI) const;
372 unsigned getMemAccessSize(const MachineInstr* MI) const;
373 int getMinValue(const MachineInstr *MI) const;
374 short getNonExtOpcode(const MachineInstr *MI) const;
376 unsigned &PredRegPos, unsigned &PredRegFlags) const;
377 short getPseudoInstrPair(const MachineInstr *MI) const;
378 short getRegForm(const MachineInstr *MI) const;
379 unsigned getSize(const MachineInstr *MI) const;
380 uint64_t getType(const MachineInstr* MI) const;
381 unsigned getUnits(const MachineInstr* MI) const;
382 unsigned getValidSubTargets(const unsigned Opcode) const;
387 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const;
388 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const;
391 void immediateExtend(MachineInstr *MI) const;
393 MachineBasicBlock* NewTarget) const;
394 void genAllInsnTimingClasses(MachineFunction &MF) const;
395 bool reversePredSense(MachineInstr* MI) const;
396 unsigned reversePrediction(unsigned Opcode) const;
397 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const;
