Lines Matching full:b00
144 def C4_cmpneq : T_ALU32_3op_cmp<"!cmp.eq", 0b00, 1, 1>;
237 def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
240 def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
311 def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
581 let Inst{27-26} = 0b00;
750 def S4_storerbnew_ap : T_ST_absset_nv <"memb", "STrib", 0b00, ByteAccess>;
837 let Inst{12-11} = 0b00;
847 def S4_storerbnew_ur : T_StoreAbsRegNV <"memb", "STrib", 0b00, ByteAccess>;
1021 ST_Idxd_shl_nv<"memb", "STrib", IntRegs, 0b00>;
1155 defm S4_storeirb : ST_Imm<"memb", "STrib", u6_0Imm, 0b00>;
1360 u6_0Ext, 0b00>, AddrModeRel;
1499 defm storerbnew: ST_PostInc_nv <"memb", "STrib", s4_0Imm, 0b00>;
1531 def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
1586 let Inst{27-26} = 0b00;
1807 def C4_and_and : T_LOGICAL_3OP<"and", "and", 0b00, 0>;
1811 def C4_and_andn : T_LOGICAL_3OP<"and", "and", 0b00, 1>;
2265 def S4_or_andi : T_CompOR <"and", 0b00, and>;
2604 def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8Imm>;
2605 def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8Imm>;
2606 def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7Imm>;
2609 def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8Imm>;
2614 def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8Imm>;
2661 defm S4_andi : T_ShiftOperate<"and", and, 0b00, ALU64_tc_2_SLOT23>;
2687 def A4_cround_rr : T_S3op_3 < "cround", IntRegs, 0b11, 0b00>;
2881 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2913 let offsetBits = !if (!eq(opcBits, 0b00), offset{5-0},
2930 def L4_add#NAME : MemOp_rr_base <opc, opcBits, ImmOp, " += ", 0b00>; // add
2938 def L4_iadd#NAME : MemOp_ri_base <opc, opcBits, ImmOp, " += ", 0b00 >;
2952 defm memopb_io : MemOp_base <"memb", 0b00, u6_0Ext>;
3170 def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
3515 defm storerb : ST_Abs <"memb", "STrib", IntRegs, u16_0Imm, 0b00>,
3516 ST_Abs_NV <"memb", "STrib", u16_0Imm, 0b00>;
3564 defm S2_storerb : ST_GP<"memb", "STrib", u16_0Imm, 0b00>, NewValueRel;
4020 let Inst{27-26} = 0b00;
4121 let Inst{27-26} = 0b00;
4125 let Inst{24-23} = !if (!eq(op, "eq"), 0b00,
4175 let Inst{27-26} = 0b00;
4184 let Inst{9-8} = !if (!eq(op, "eq"), 0b00,
