Lines Matching full:slot1
19 // | SLOT1 | LD ST ALU32 |
28 def SLOT1 : FuncUnit;
100 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
103 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
105 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
107 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
111 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
113 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
137 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
151 InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
176 InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
177 InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
179 InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
180 InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
189 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
192 InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
