Lines Matching full:slot1
19 // | SLOT1 | LD ST ALU32 |
43 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
46 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
48 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
50 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
52 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
54 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
56 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
83 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
86 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
99 InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
108 InstrItinData<SUBINSN_tc_1_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
110 [InstrStage<2, [SLOT0, SLOT1]>]>,
111 InstrItinData<SUBINSN_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
112 InstrItinData<SUBINSN_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
131 InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>,
132 InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
134 InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
135 InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
142 [InstrStage<3, [SLOT0, SLOT1]>]>,
148 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
154 InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
155 InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
