Lines Matching full:slot1
69 // | SLOT1 | LD ST ALU32 |
107 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
112 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
114 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
116 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
118 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
120 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
122 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
149 [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
152 InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
165 InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
174 InstrItinData<SUBINSN_tc_1_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
176 [InstrStage<2, [SLOT0, SLOT1]>]>,
177 InstrItinData<SUBINSN_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
178 InstrItinData<SUBINSN_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
198 InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>,
199 InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
201 InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
202 InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
209 [InstrStage<3, [SLOT0, SLOT1]>]>,
215 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
222 InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
223 InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
228 InstrItinData<CVI_VA,[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
232 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
249 InstrItinData<CVI_VP, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
251 InstrItinData<CVI_VP_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
254 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
257 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
260 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
263 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
265 InstrItinData<CVI_VP_DV , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
268 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
271 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
273 InstrItinData<CVI_VM_LD , [InstrStage<1, [SLOT0, SLOT1], 0>,
277 InstrItinData<CVI_VM_TMP_LD,[InstrStage<1,[SLOT0, SLOT1], 0>,
279 InstrItinData<CVI_VM_CUR_LD,[InstrStage<1,[SLOT0, SLOT1], 0>,
284 InstrStage<1, [SLOT1], 0>,
294 InstrStage<1, [SLOT1], 0>,
297 InstrItinData<CVI_HIST , [InstrStage<1, [SLOT0,SLOT1
