Lines Matching defs:DestReg
119 bool emitCmp(unsigned DestReg, const CmpInst *CI);
127 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
130 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
134 unsigned DestReg);
136 unsigned DestReg);
334 unsigned DestReg = createResultReg(RC);
336 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
337 return DestReg;
340 unsigned DestReg = createResultReg(RC);
344 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
345 return DestReg;
355 unsigned DestReg = createResultReg(RC);
361 emitInst(Mips::LW, DestReg)
368 .addReg(DestReg)
370 DestReg = TempReg;
372 return DestReg;
377 unsigned DestReg = createResultReg(RC);
378 emitInst(Mips::LW, DestReg)
381 return DestReg;
951 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
952 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
953 updateValueMap(I, DestReg);
1023 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1024 if (!DestReg)
1027 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1028 DestReg);
1061 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1067 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1069 updateValueMap(I, DestReg);
1343 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1344 if (DestReg == 0)
1348 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1349 updateValueMap(II, DestReg);
1361 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1362 updateValueMap(II, DestReg);
1369 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1370 updateValueMap(II, DestReg);
1390 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1391 updateValueMap(II, DestReg);
1469 unsigned DestReg = VA.getLocReg();
1471 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1501 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1563 unsigned DestReg) {
1577 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1582 unsigned DestReg) {
1587 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1590 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1597 unsigned DestReg) {
1601 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1602 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1606 unsigned DestReg) {
1623 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1628 unsigned DestReg, bool IsZExt) {
1637 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1638 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1643 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1644 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1645 return Success ? DestReg : 0;
1846 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1847 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1848 Addr.setReg(DestReg);
