Lines Matching refs:isZExt
155 bool isZExt, unsigned DestReg);
157 const TargetRegisterClass *RC, bool IsZExt = true,
164 unsigned DestReg, bool IsZExt);
451 bool IsZExt, unsigned FP64LoadOpc) {
479 Opc = (IsZExt ?
484 Opc = (IsZExt ?
801 bool IsZExt, unsigned DestReg) {
824 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
825 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
847 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
849 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
853 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
855 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
872 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
878 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
1337 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1349 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1700 unsigned DestReg, bool IsZExt) {
1707 if (!IsZExt) {
1802 bool IsZExt = isa<ZExtInst>(I);
1828 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
2181 bool IsZExt = false;
2188 IsZExt = true;
2199 IsZExt = true;
2236 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt))
