Lines Matching full:ppc
1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
99 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
102 static const SpillSlot darwinOffsets = {PPC::R31, -4};
118 {PPC::F31, -8},
119 {PPC::F30, -16},
120 {PPC::F29, -24},
121 {PPC::F28, -32},
122 {PPC::F27, -40},
123 {PPC::F26, -48},
124 {PPC::F25, -56},
125 {PPC::F24, -64},
126 {PPC::F23, -72},
127 {PPC::F22, -80},
128 {PPC::F21, -88},
129 {PPC::F20, -96},
130 {PPC::F19, -104},
131 {PPC::F18, -112},
132 {PPC::F17, -120},
133 {PPC::F16, -128},
134 {PPC::F15, -136},
135 {PPC::F14, -144},
138 {PPC::R31, -4},
139 {PPC::R30, -8},
140 {PPC::R29, -12},
141 {PPC::R28, -16},
142 {PPC::R27, -20},
143 {PPC::R26, -24},
144 {PPC::R25, -28},
145 {PPC::R24, -32},
146 {PPC::R23, -36},
147 {PPC::R22, -40},
148 {PPC::R21, -44},
149 {PPC::R20, -48},
150 {PPC::R19, -52},
151 {PPC::R18, -56},
152 {PPC::R17, -60},
153 {PPC::R16, -64},
154 {PPC::R15, -68},
155 {PPC::R14, -72},
161 {PPC::CR2, -4},
164 {PPC::VRSAVE, -4},
167 {PPC::V31, -16},
168 {PPC::V30, -32},
169 {PPC::V29, -48},
170 {PPC::V28, -64},
171 {PPC::V27, -80},
172 {PPC::V26, -96},
173 {PPC::V25, -112},
174 {PPC::V24, -128},
175 {PPC::V23, -144},
176 {PPC::V22, -160},
177 {PPC::V21, -176},
178 {PPC::V20, -192}};
182 {PPC::F31, -8},
183 {PPC::F30, -16},
184 {PPC::F29, -24},
185 {PPC::F28, -32},
186 {PPC::F27, -40},
187 {PPC::F26, -48},
188 {PPC::F25, -56},
189 {PPC::F24, -64},
190 {PPC::F23, -72},
191 {PPC::F22, -80},
192 {PPC::F21, -88},
193 {PPC::F20, -96},
194 {PPC::F19, -104},
195 {PPC::F18, -112},
196 {PPC::F17, -120},
197 {PPC::F16, -128},
198 {PPC::F15, -136},
199 {PPC::F14, -144},
202 {PPC::X31, -8},
203 {PPC::X30, -16},
204 {PPC::X29, -24},
205 {PPC::X28, -32},
206 {PPC::X27, -40},
207 {PPC::X26, -48},
208 {PPC::X25, -56},
209 {PPC::X24, -64},
210 {PPC::X23, -72},
211 {PPC::X22, -80},
212 {PPC::X21, -88},
213 {PPC::X20, -96},
214 {PPC::X19, -104},
215 {PPC::X18, -112},
216 {PPC::X17, -120},
217 {PPC::X16, -128},
218 {PPC::X15, -136},
219 {PPC::X14, -144},
222 {PPC::VRSAVE, -4},
225 {PPC::V31, -16},
226 {PPC::V30, -32},
227 {PPC::V29, -48},
228 {PPC::V28, -64},
229 {PPC::V27, -80},
230 {PPC::V26, -96},
231 {PPC::V25, -112},
232 {PPC::V24, -128},
233 {PPC::V23, -144},
234 {PPC::V22, -160},
235 {PPC::V21, -176},
236 {PPC::V20, -192}};
265 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
277 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
293 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
334 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
353 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
357 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
362 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
366 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
371 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
375 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
379 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
522 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
523 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
529 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
541 case PPC::FP:
544 case PPC::FP8:
547 case PPC::BP:
550 case PPC::BP8:
563 unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
591 unsigned Reg = RS.FindUnusedReg(Subtarget.isPPC64() ? &PPC::G8RCRegClass
592 : &PPC::GPRCRegClass);
645 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
671 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
673 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
674 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
676 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
678 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
679 : PPC::MFLR );
680 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
681 : PPC::STW );
682 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
683 : PPC::STWU );
684 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
685 : PPC::STWUX);
686 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
687 : PPC::LIS );
688 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
689 : PPC::ORI );
690 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
691 : PPC::OR );
692 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
693 : PPC::SUBFC);
694 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
695 : PPC::SUBFIC);
762 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
777 .addReg(PPC::R30)
796 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
816 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
821 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
894 unsigned Reg = MRI->getDwarfRegNum(PPC::R30, true);
944 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
948 if (PPC::CRBITRCRegClass.contains(Reg))
953 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
959 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
963 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
1012 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1014 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1016 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1017 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1018 : PPC::MTLR );
1019 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1020 : PPC::LWZ );
1021 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1022 : PPC::LIS );
1023 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1024 : PPC::ORI );
1025 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1026 : PPC::ADDI );
1027 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1028 : PPC::ADD4 );
1072 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
1073 RetOpcode == PPC::TCRETURNdi ||
1074 RetOpcode == PPC::TCRETURNai ||
1075 RetOpcode == PPC::TCRETURNri8 ||
1076 RetOpcode == PPC::TCRETURNdi8 ||
1077 RetOpcode == PPC::TCRETURNai8;
1142 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1154 .addReg(PPC::R30)
1165 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1176 (RetOpcode == PPC::BLR || RetOpcode == PPC::BLR8) &&
1195 } else if (RetOpcode == PPC::TCRETURNdi) {
1198 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1200 } else if (RetOpcode == PPC::TCRETURNri) {
1203 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1204 } else if (RetOpcode == PPC::TCRETURNai) {
1207 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1208 } else if (RetOpcode == PPC::TCRETURNdi8) {
1211 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1213 } else if (RetOpcode == PPC::TCRETURNri8) {
1216 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1217 } else if (RetOpcode == PPC::TCRETURNai8) {
1220 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1281 (SavedRegs.test(PPC::CR2) ||
1282 SavedRegs.test(PPC::CR3) ||
1283 SavedRegs.test(PPC::CR4))) {
1307 unsigned MinGPR = PPC::R31;
1308 unsigned MinG8R = PPC::X31;
1309 unsigned MinFPR = PPC::F31;
1310 unsigned MinVR = PPC::V31;
1325 if (PPC::GPRCRegClass.contains(Reg)) {
1333 } else if (PPC::G8RCRegClass.contains(Reg)) {
1341 } else if (PPC::F8RCRegClass.contains(Reg)) {
1349 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1350 PPC::CRRCRegClass.contains(Reg)) {
1352 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
1354 } else if (PPC::VRRCRegClass.contains(Reg)) {
1462 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
1465 (PPC::CRBITRCRegClass.contains(Reg) ||
1466 PPC::CRRCRegClass.contains(Reg)))) {
1483 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1527 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1528 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1570 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1574 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1596 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
1600 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1601 .addReg(PPC::R12,
1630 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1631 PPC::R12),
1633 RestoreOp = PPC::MTOCRF;
1634 MoveReg = PPC::R12;
1638 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1642 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1646 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1655 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1660 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1661 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1662 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1663 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1664 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1665 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1723 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1726 if (Reg == PPC::CR2) {
1732 } else if (Reg == PPC::CR3) {
1735 } else if (Reg == PPC::CR4) {
1742 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
