Lines Matching refs:isPPC64
42 return STI.isPPC64() ? 16 : 8;
44 return STI.isPPC64() ? 16 : 4;
58 return STI.isPPC64() ? -8U : -4U;
61 return STI.isPPC64() ? -8U : -4U;
65 if (STI.isDarwinABI() || STI.isPPC64())
66 return (STI.isELFv2ABI() ? 4 : 6) * (STI.isPPC64() ? 8 : 4);
74 return STI.isPPC64() ? -16U : -8U;
77 return STI.isPPC64()
98 if (Subtarget.isPPC64()) {
238 if (Subtarget.isPPC64()) {
449 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
563 unsigned R0 = Subtarget.isPPC64() ? PPC::X0 : PPC::R0;
591 unsigned Reg = RS.FindUnusedReg(Subtarget.isPPC64() ? &PPC::G8RCRegClass
634 bool isPPC64 = Subtarget.isPPC64();
671 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
673 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
674 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
676 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
678 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
680 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
682 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
684 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
686 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
688 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
690 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
692 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
694 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
701 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
754 assert((isPPC64 || MustSaveCRs.empty()) &&
815 if (isPPC64)
959 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1000 bool isPPC64 = Subtarget.isPPC64();
1012 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
1014 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
1016 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
1017 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
1019 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
1021 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
1023 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
1025 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
1027 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
1138 assert((isPPC64 || MustSaveCRs.empty()) &&
1241 bool isPPC64 = Subtarget.isPPC64();
1250 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
1259 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1280 if (!isPPC64 && !isDarwinABI &&
1445 if (Subtarget.isPPC64()) {
1457 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
1529 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1587 if (Subtarget.isPPC64()) {
1615 restoreCRs(bool isPPC64, bool is31,
1625 if (isPPC64)
1658 bool is64Bit = Subtarget.isPPC64();
1744 restoreCRs(Subtarget.isPPC64(), is31,
1770 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
1779 MF.getSubtarget<PPCSubtarget>().isPPC64());
