Lines Matching refs:RegKind
92 // MemKind says what type of memory this is and RegKind says what type
99 unsigned RegKind : 4;
165 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base,
170 Op->Mem.RegKind = RegKind;
199 bool isReg(RegisterKind RegKind) const {
200 return Kind == KindReg && Reg.Kind == RegKind;
241 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const {
242 return isMem(MemKind) && Mem.RegKind == RegKind;
244 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const {
245 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff);
247 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const {
248 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287);
250 bool isMemDisp12Len8(RegisterKind RegKind) const {
251 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length, 1, 0x100);
376 const unsigned *Regs, RegisterKind RegKind);
380 RegisterKind RegKind);
573 // Regs maps asm register numbers to LLVM register numbers and RegKind
578 RegisterKind RegKind) {
621 if (parseRegister(Reg, RegGR, Regs, RegKind))
638 const unsigned *Regs, RegisterKind RegKind) {
644 if (parseAddress(Base, Disp, Index, IsVector, Length, Regs, RegKind))
674 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
