Lines Matching full:srcreg
126 unsigned SrcReg = MI->getOperand(1).getReg();
128 bool SrcIsHigh = isHighReg(SrcReg);
133 DestReg, SrcReg, SystemZ::LR, 32,
163 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
164 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
166 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
167 // KillSrc is true if this move is the last use of SrcReg.
171 unsigned SrcReg, unsigned LowLowOpcode,
175 bool SrcIsHigh = isHighReg(SrcReg);
184 .addReg(SrcReg, getKillRegState(KillSrc));
190 .addReg(SrcReg, getKillRegState(KillSrc))
406 unsigned &SrcReg, unsigned &SrcReg2,
413 SrcReg = MI->getOperand(0).getReg();
444 // Compare compares SrcReg against zero. Check whether SrcReg contains
448 static bool removeIPMBasedCompare(MachineInstr *Compare, unsigned SrcReg,
452 MachineInstr *RLL = getDef(SrcReg, MRI);
490 unsigned SrcReg, unsigned SrcReg2,
496 removeIPMBasedCompare(Compare, SrcReg, MRI, &RI);
554 unsigned SrcReg, bool KillSrc) const {
556 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
558 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
560 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
564 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
565 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
571 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
573 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
575 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
577 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
579 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
581 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
583 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
589 .addReg(SrcReg, getKillRegState(KillSrc));
593 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
603 .addReg(SrcReg, getKillRegState(isKill)),
693 unsigned SrcReg = Src.getReg();
699 TargetRegisterInfo::isVirtualRegister(SrcReg) &&
701 MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
703 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
