Lines Matching full:v8i64
1311 addRegisterClass(MVT::v8i64, &X86::VR512RegClass);
1327 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1328 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Legal);
1329 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1330 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i16, Legal);
1331 setLoadExtAction(ISD::ZEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1332 setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i32, Legal);
1345 setOperationAction(ISD::LOAD, MVT::v8i64, Legal);
1384 setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);
1385 setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);
1386 setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);
1416 setOperationAction(ISD::SINT_TO_FP, MVT::v8i64, Legal);
1417 setOperationAction(ISD::UINT_TO_FP, MVT::v8i64, Legal);
1418 setOperationAction(ISD::FP_TO_SINT, MVT::v8i64, Legal);
1419 setOperationAction(ISD::FP_TO_UINT, MVT::v8i64, Legal);
1445 setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
1447 setOperationAction(ISD::ANY_EXTEND, MVT::v8i64, Custom);
1449 setOperationAction(ISD::SIGN_EXTEND, MVT::v8i64, Custom);
1469 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i64, Custom);
1477 setOperationAction(ISD::MUL, MVT::v8i64, Custom);
1487 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1493 setOperationAction(ISD::SMAX, MVT::v8i64, Legal);
1495 setOperationAction(ISD::UMAX, MVT::v8i64, Legal);
1497 setOperationAction(ISD::SMIN, MVT::v8i64, Legal);
1499 setOperationAction(ISD::UMIN, MVT::v8i64, Legal);
1501 setOperationAction(ISD::ADD, MVT::v8i64, Legal);
1504 setOperationAction(ISD::SUB, MVT::v8i64, Legal);
1509 setOperationAction(ISD::SRL, MVT::v8i64, Custom);
1512 setOperationAction(ISD::SHL, MVT::v8i64, Custom);
1515 setOperationAction(ISD::SRA, MVT::v8i64, Custom);
1518 setOperationAction(ISD::AND, MVT::v8i64, Legal);
1519 setOperationAction(ISD::OR, MVT::v8i64, Legal);
1520 setOperationAction(ISD::XOR, MVT::v8i64, Legal);
1526 setOperationAction(ISD::CTLZ, MVT::v8i64, Legal);
1528 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::v8i64, Legal);
1540 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i64, Custom);
1572 setOperationAction(ISD::MUL, MVT::v8i64, Legal);
1614 AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);
1694 AddPromotedToType (ISD::AND, VT, MVT::v8i64);
1696 AddPromotedToType (ISD::OR, VT, MVT::v8i64);
1698 AddPromotedToType (ISD::XOR, VT, MVT::v8i64);
11062 assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11063 assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");
11069 lowerV4X128VectorShuffle(DL, MVT::v8i64, Mask, V1, V2, DAG))
11073 lowerVectorShuffleWithUNPCK(DL, MVT::v8i64, Mask, V1, V2, DAG))
11076 return lowerVectorShuffleWithPERMV(DL, MVT::v8i64, Mask, V1, V2, DAG);
11156 case MVT::v8i64:
11200 ExtVT = MVT::v8i64; // Take 512-bit type, more shuffles on KNL
11562 MVT ExtVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
11706 MVT ExtVecVT = (VecVT == MVT::v8i1 ? MVT::v8i64 : MVT::v16i32);
13221 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
13301 MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;
15125 MVT ExtVT = NumElts == 8 ? MVT::v8i64 : MVT::v16i32;
18090 assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&
18091 "Only know how to lower V2I64/V4I64/V8I64 multiply");
19854 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19863 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19969 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
19982 Index = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i64, Index);
28398 case MVT::v8i64:
