Lines Matching full:srcreg
2043 unsigned &SrcReg, unsigned &DstReg,
2063 SrcReg = MI.getOperand(1).getReg();
2551 unsigned SrcReg = Src.getReg();
2556 NewSrc = SrcReg;
2569 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2583 isKill = MI->killsRegister(SrcReg);
2781 unsigned SrcReg;
2784 SrcReg, isKill, isUndef, ImplicitOp))
2790 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2816 unsigned SrcReg;
2819 SrcReg, isKill, isUndef, ImplicitOp))
2824 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2846 unsigned SrcReg;
2849 SrcReg, isKill, isUndef, ImplicitOp))
2854 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2882 unsigned SrcReg;
2885 SrcReg, isKill, isUndef, ImplicitOp))
2903 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2952 unsigned SrcReg;
2955 SrcReg, isKill, isUndef, ImplicitOp))
2960 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
4249 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
4252 // SrcReg(VR128) -> DestReg(GR64)
4253 // SrcReg(VR64) -> DestReg(GR64)
4254 // SrcReg(GR64) -> DestReg(VR128)
4255 // SrcReg(GR64) -> DestReg(VR64)
4260 if (X86::VR128XRegClass.contains(SrcReg))
4264 if (X86::VR64RegClass.contains(SrcReg))
4267 } else if (X86::GR64RegClass.contains(SrcReg)) {
4277 // SrcReg(FR32) -> DestReg(GR32)
4278 // SrcReg(GR32) -> DestReg(FR32)
4280 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
4284 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4305 unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4306 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
4310 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
4311 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
4318 unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4319 if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4321 if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4323 if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4325 if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4327 if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4333 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4337 if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4340 if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4342 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
4343 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
4344 X86::VR512RegClass.contains(DestReg, SrcReg)) {
4346 SrcReg = get512BitSuperRegister(SrcReg);
4349 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
4351 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
4352 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
4355 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
4364 unsigned DestReg, unsigned SrcReg,
4370 if (X86::GR64RegClass.contains(DestReg, SrcReg))
4372 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4374 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4376 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4379 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
4383 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4388 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4391 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
4392 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
4394 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4397 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
4401 .addReg(SrcReg, getKillRegState(KillSrc));
4405 bool FromEFLAGS = SrcReg == X86::EFLAGS;
4407 int Reg = FromEFLAGS ? DestReg : SrcReg;
4431 .addReg(SrcReg, getKillRegState(KillSrc));
4487 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4609 static unsigned getStoreRegOpcode(unsigned SrcReg,
4613 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
4626 unsigned SrcReg, bool isKill, int FrameIdx,
4636 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4639 .addReg(SrcReg, getKillRegState(isKill));
4642 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4652 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
4657 MIB.addReg(SrcReg, getKillRegState(isKill));
4697 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4708 SrcReg = MI->getOperand(0).getReg();
4718 SrcReg = MI->getOperand(1).getReg();
4727 SrcReg = MI->getOperand(1).getReg();
4739 SrcReg = MI->getOperand(1).getReg();
4748 SrcReg = MI->getOperand(0).getReg();
4757 SrcReg = MI->getOperand(0).getReg();
4758 if (MI->getOperand(1).getReg() != SrcReg) return false;
4772 /// SrcReg, SrcRegs: register operands for FlagI.
4774 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4785 ((OI->getOperand(1).getReg() == SrcReg &&
4788 OI->getOperand(2).getReg() == SrcReg)))
4805 OI->getOperand(1).getReg() == SrcReg &&
4920 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4972 // Get the unique definition of SrcReg.
4973 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4997 J->getOperand(1).getReg() == SrcReg) {
5000 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5031 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
5059 Sub->getOperand(2).getReg() == SrcReg);
