Lines Matching full:zeroinitializer
121 ; CHECK-NEXT: ret <8 x i16> zeroinitializer
143 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
165 ; CHECK-NEXT: ret <2 x i64> zeroinitializer
187 ; CHECK-NEXT: ret <16 x i16> zeroinitializer
209 ; CHECK-NEXT: ret <8 x i32> zeroinitializer
231 ; CHECK-NEXT: ret <4 x i64> zeroinitializer
257 ; CHECK-NEXT: ret <8 x i16> zeroinitializer
279 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
301 ; CHECK-NEXT: ret <2 x i64> zeroinitializer
323 ; CHECK-NEXT: ret <16 x i16> zeroinitializer
345 ; CHECK-NEXT: ret <8 x i32> zeroinitializer
367 ; CHECK-NEXT: ret <4 x i64> zeroinitializer
379 %1 = tail call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %v, <8 x i16> zeroinitializer)
410 %1 = tail call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %v, <4 x i32> zeroinitializer)
441 %1 = tail call <16 x i16> @llvm.x86.avx2.psra.w(<16 x i16> %v, <8 x i16> zeroinitializer)
472 %1 = tail call <8 x i32> @llvm.x86.avx2.psra.d(<8 x i32> %v, <4 x i32> zeroinitializer)
507 %1 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %v, <8 x i16> zeroinitializer)
521 ; CHECK-NEXT: ret <8 x i16> zeroinitializer
528 ; CHECK-NEXT: ret <8 x i16> zeroinitializer
536 %1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> zeroinitializer)
550 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
557 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
565 %1 = tail call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %v, <2 x i64> zeroinitializer)
579 ; CHECK-NEXT: ret <2 x i64> zeroinitializer
587 %1 = tail call <16 x i16> @llvm.x86.avx2.psrl.w(<16 x i16> %v, <8 x i16> zeroinitializer)
601 ; CHECK-NEXT: ret <16 x i16> zeroinitializer
608 ; CHECK-NEXT: ret <16 x i16> zeroinitializer
616 %1 = tail call <8 x i32> @llvm.x86.avx2.psrl.d(<8 x i32> %v, <4 x i32> zeroinitializer)
630 ; CHECK-NEXT: ret <8 x i32> zeroinitializer
637 ; CHECK-NEXT: ret <8 x i32> zeroinitializer
645 %1 = tail call <4 x i64> @llvm.x86.avx2.psrl.q(<4 x i64> %v, <2 x i64> zeroinitializer)
659 ; CHECK-NEXT: ret <4 x i64> zeroinitializer
671 %1 = tail call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %v, <8 x i16> zeroinitializer)
685 ; CHECK-NEXT: ret <8 x i16> zeroinitializer
692 ; CHECK-NEXT: ret <8 x i16> zeroinitializer
700 %1 = tail call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %v, <4 x i32> zeroinitializer)
714 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
721 ; CHECK-NEXT: ret <4 x i32> zeroinitializer
729 %1 = tail call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %v, <2 x i64> zeroinitializer)
743 ; CHECK-NEXT: ret <2 x i64> zeroinitializer
751 %1 = tail call <16 x i16> @llvm.x86.avx2.psll.w(<16 x i16> %v, <8 x i16> zeroinitializer)
765 ; CHECK-NEXT: ret <16 x i16> zeroinitializer
772 ; CHECK-NEXT: ret <16 x i16> zeroinitializer
780 %1 = tail call <8 x i32> @llvm.x86.avx2.psll.d(<8 x i32> %v, <4 x i32> zeroinitializer)
794 ; CHECK-NEXT: ret <8 x i32> zeroinitializer
801 ; CHECK-NEXT: ret <8 x i32> zeroinitializer
809 %1 = tail call <4 x i64> @llvm.x86.avx2.psll.q(<4 x i64> %v, <2 x i64> zeroinitializer)
823 ; CHECK-NEXT: ret <4 x i64> zeroinitializer
1166 ; CHECK: ret <2 x i64> zeroinitializer
1189 ; CHECK: ret <4 x i64> zeroinitializer
1257 ; CHECK: ret <2 x i64> zeroinitializer
1280 ; CHECK: ret <4 x i64> zeroinitializer
