Lines Matching refs:ProcModel
416 const CodeGenProcModel &ProcModel) const {
425 if (&getProcModel(ModelDef) != &ProcModel)
430 "defined for processor " + ProcModel.ModelName +
436 RWSeq, IsRead,ProcModel);
448 expandRWSeqForProc(*I, RWSeq, IsRead, ProcModel);
556 const CodeGenProcModel &ProcModel =
558 ProcIndices.push_back(ProcModel.Index);
559 dbgs() << "InstRW on " << ProcModel.ModelName << " for " << InstName;
771 for (CodeGenProcModel &ProcModel : ProcModels) {
772 if (!ProcModel.hasItineraries())
775 RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");
776 assert(!ItinRecords.empty() && "ProcModel.hasItineraries is incorrect");
779 ProcModel.ItinDefList.resize(NumInstrSchedClasses);
791 ProcModel.ItinDefList[SCI->Index] = ItinData;
796 DEBUG(dbgs() << ProcModel.ItinsDef->getName()
801 assert(!ProcModel.ItinDefList[0] && "NoItinerary class can't have rec");
803 for (unsigned i = 1, N = ProcModel.ItinDefList.size(); i < N; ++i) {
804 if (!ProcModel.ItinDefList[i])
805 dbgs() << ProcModel.ItinsDef->getName()
1489 // Finalize each ProcModel by sorting the record arrays.
