Lines Matching refs:SchedClasses
123 // Infer new SchedClasses from SchedVariant.
197 // More may be inferred later when inferring new SchedClasses from variants.
489 /// SchedClasses. More SchedClasses may be inferred.
493 SchedClasses.resize(1);
494 SchedClasses.back().Index = 0;
495 SchedClasses.back().Name = "NoInstrModel";
496 SchedClasses.back().ItinClassDef = Records.getDef("NoItinerary");
497 SchedClasses.back().ProcIndices.push_back(0);
519 NumInstrSchedClasses = SchedClasses.size();
553 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;
641 if (Idx || SchedClasses[0].isKeyEqual(ItinClassDef, OperWrites, OperReads)) {
643 std::set_union(SchedClasses[Idx].ProcIndices.begin(),
644 SchedClasses[Idx].ProcIndices.end(),
647 SchedClasses[Idx].ProcIndices.swap(PI);
650 Idx = SchedClasses.size();
651 SchedClasses.resize(Idx+1);
652 CodeGenSchedClass &SC = SchedClasses.back();
701 const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;
711 assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 &&
714 << SchedClasses[OldSCIdx].Name << " on "
716 SchedClasses[OldSCIdx].InstRWs.push_back(InstRWDef);
721 unsigned SCIdx = SchedClasses.size();
722 SchedClasses.resize(SCIdx+1);
723 CodeGenSchedClass &SC = SchedClasses.back();
730 SC.ItinClassDef = SchedClasses[OldSCIdx].ItinClassDef;
731 SC.Writes = SchedClasses[OldSCIdx].Writes;
732 SC.Reads = SchedClasses[OldSCIdx].Reads;
742 for (RecIter RI = SchedClasses[OldSCIdx].InstRWs.begin(),
743 RE = SchedClasses[OldSCIdx].InstRWs.end(); RI != RE; ++RI) {
789 // Multiple SchedClasses may share an itinerary. Update all of them.
807 << SchedClasses[i].Name << '\n';
835 for (unsigned Idx = 0; Idx != SchedClasses.size(); ++Idx) {
836 assert(SchedClasses[Idx].Index == Idx && "bad SCIdx");
838 SchedClasses[Idx].ItinClassDef)
839 inferFromItinClass(SchedClasses[Idx].ItinClassDef, Idx);
840 if (!SchedClasses[Idx].InstRWs.empty())
842 if (!SchedClasses[Idx].Writes.empty()) {
843 inferFromRW(SchedClasses[Idx].Writes, SchedClasses[Idx].Reads,
844 Idx, SchedClasses[Idx].ProcIndices);
846 assert(SchedClasses.size() < (NumInstrSchedClasses*6) &&
878 for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) {
879 assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!");
880 Record *Rec = SchedClasses[SCIdx].InstRWs[I];
895 inferFromRW(Writes, Reads, SCIdx, ProcIndices); // May mutate SchedClasses.
1317 // Create new SchedClasses for the given ReadWrite list. If any of the
1372 // WARNING: We are about to mutate the SchedClasses vector. Do not refer to
