Lines Matching full:processor
36 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
219 // Gather and sort processor information
221 Records.getAllDerivedDefinitions("Processor");
224 // Begin processor table
229 // For each processor
231 // Next processor
232 Record *Processor = ProcessorList[i];
234 const std::string &Name = Processor->getValueAsString("Name");
236 Processor->getValueAsListOfDefs("Features");
241 << "\"Select the " << Name << " processor\", ";
263 // End processor table
364 // Multiple processor models may share an itinerary record. Emit it once.
429 // If this processor defines no itineraries, then leave the itinerary list
531 // EmitProcessorData - Generate data for processor itineraries that were
533 // Itineraries for each processor. The Itinerary lists are indexed on
540 // Multiple processor models may share an itinerary record. Emit it once.
543 // For each processor's machine model
553 // Get processor itinerary name
556 // Get the itinerary list for the processor.
568 // Begin processor itinerary table
585 // End processor itinerary table
592 // value defined in the C++ header. The Record is null if the processor does not
652 // Find the WriteRes Record that defines processor resources for this
658 // specifies a set of processor resources.
674 "defined for processor " + ProcModel.ModelName +
681 // Check this processor's list of write resources.
691 "SchedWrite and its alias on processor " +
697 // TODO: If ProcModel has a base model (previous generation processor),
701 std::string("Processor does not define resources for ")
707 /// Find the ReadAdvance record for the given SchedRead on this processor or
715 // Check this processor's list of aliases for SchedRead.
728 "defined for processor " + ProcModel.ModelName +
735 // Check this processor's ReadAdvanceList.
745 "SchedRead and its alias on processor " +
751 // TODO: If ProcModel has a base model (previous generation processor),
755 std::string("Processor does not define resources for ")
761 // Expand an explicit list of processor resources into a full list of implied
780 PrintFatalError(SubDef->getLoc(), "Processor resource group "
811 // Generate the SchedClass table for this processor and update global
812 // tables. Must be called for each processor in order.
855 // Determine if the SchedClass is actually reachable on this processor. If
856 // not don't try to locate the processor resources, it will fail.
887 // Check this processor's itinerary class resources.
1121 // Emit a SchedClass table for each processor.
1166 // For each processor model.
1169 // Emit processor resource table.
1176 // Begin processor itinerary properties
1194 OS << " " << PI->Index << ", // Processor ID\n";
1215 // Gather and sort processor information
1217 Records.getAllDerivedDefinitions("Processor");
1220 // Begin processor table
1226 // For each processor
1228 // Next processor
1229 Record *Processor = ProcessorList[i];
1231 const std::string &Name = Processor->getValueAsString("Name");
1233 SchedModels.getModelForProc(Processor).ModelName;
1244 // End processor table
1277 // Emit the processor machine model
1279 // Emit the processor lookup data
