Lines Matching refs:src1
1419 void Assembler::and_(Register dst, Register src1, const Operand& src2,
1421 addrmod1(cond | AND | s, src1, dst, src2);
1425 void Assembler::eor(Register dst, Register src1, const Operand& src2,
1427 addrmod1(cond | EOR | s, src1, dst, src2);
1431 void Assembler::sub(Register dst, Register src1, const Operand& src2,
1433 addrmod1(cond | SUB | s, src1, dst, src2);
1437 void Assembler::rsb(Register dst, Register src1, const Operand& src2,
1439 addrmod1(cond | RSB | s, src1, dst, src2);
1443 void Assembler::add(Register dst, Register src1, const Operand& src2,
1445 addrmod1(cond | ADD | s, src1, dst, src2);
1449 void Assembler::adc(Register dst, Register src1, const Operand& src2,
1451 addrmod1(cond | ADC | s, src1, dst, src2);
1455 void Assembler::sbc(Register dst, Register src1, const Operand& src2,
1457 addrmod1(cond | SBC | s, src1, dst, src2);
1461 void Assembler::rsc(Register dst, Register src1, const Operand& src2,
1463 addrmod1(cond | RSC | s, src1, dst, src2);
1467 void Assembler::tst(Register src1, const Operand& src2, Condition cond) {
1468 addrmod1(cond | TST | S, src1, r0, src2);
1472 void Assembler::teq(Register src1, const Operand& src2, Condition cond) {
1473 addrmod1(cond | TEQ | S, src1, r0, src2);
1477 void Assembler::cmp(Register src1, const Operand& src2, Condition cond) {
1478 addrmod1(cond | CMP | S, src1, r0, src2);
1489 void Assembler::cmn(Register src1, const Operand& src2, Condition cond) {
1490 addrmod1(cond | CMN | S, src1, r0, src2);
1494 void Assembler::orr(Register dst, Register src1, const Operand& src2,
1496 addrmod1(cond | ORR | s, src1, dst, src2);
1563 void Assembler::bic(Register dst, Register src1, const Operand& src2,
1565 addrmod1(cond | BIC | s, src1, dst, src2);
1575 void Assembler::mla(Register dst, Register src1
1577 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
1579 src2.code()*B8 | B7 | B4 | src1.code());
1583 void Assembler::mls(Register dst, Register src1, Register src2, Register srcA,
1585 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
1588 src2.code()*B8 | B7 | B4 | src1.code());
1592 void Assembler::sdiv(Register dst, Register src1, Register src2,
1594 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1597 src2.code()*B8 | B4 | src1.code());
1601 void Assembler::udiv(Register dst, Register src1, Register src2,
1603 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1606 src2.code() * B8 | B4 | src1.code());
1610 void Assembler::mul(Register dst, Register src1, Register src2, SBit s,
1612 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1614 emit(cond | s | dst.code() * B16 | src2.code() * B8 | B7 | B4 | src1.code());
1618 void Assembler::smmla(Register dst, Register src1, Register src2, Register srcA,
1620 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc) && !srcA.is(pc));
1622 srcA.code() * B12 | src2.code() * B8 | B4 | src1.code());
1626 void Assembler::smmul(Register dst, Register src1, Register src2,
1628 DCHECK(!dst.is(pc) && !src1.is(pc) && !src2.is(pc));
1630 src2.code() * B8 | B4 | src1.code());
1636 Register src1,
1640 DCHECK(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1643 src2.code()*B8 | B7 | B4 | src1.code());
1649 Register src1,
1653 DCHECK(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1656 src2.code()*B8 | B7 | B4 | src1.code());
1662 Register src1,
1666 DCHECK(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1669 src2.code()*B8 | B7 | B4 | src1.code());
1675 Register src1,
1679 DCHECK(!dstL.is(pc) && !dstH.is(pc) && !src1.is(pc) && !src2.is(pc));
1682 src2.code()*B8 | B7 | B4 | src1.code());
1796 Register src1,
1803 DCHECK(!src1.is(pc));
1809 emit(cond | 0x68*B20 | src1.code()*B16 | dst.code()*B12 |
1815 Register src1,
1822 DCHECK(!src1.is(pc));
1829 emit(cond | 0x68*B20 | src1.code()*B16 | dst.code()*B12 |
1846 void Assembler::sxtab(Register dst, Register src1, Register src2, int rotate,
1852 DCHECK(!src1.is(pc));
1855 emit(cond | 0x6A * B20 | src1.code() * B16 | dst.code() * B12 |
1872 void Assembler::sxtah(Register dst, Register src1, Register src2, int rotate,
1878 DCHECK(!src1.is(pc));
1881 emit(cond | 0x6B * B20 | src1.code() * B16 | dst.code() * B12 |
1898 void Assembler::uxtab(Register dst, Register src1, Register src2, int rotate,
1904 DCHECK(!src1.is(pc));
1907 emit(cond | 0x6E * B20 | src1.code() * B16 | dst.code() * B12 |
1936 void Assembler::uxtah(Register dst, Register src1, Register src2, int rotate,
1942 DCHECK(!src1.is(pc));
1945 emit(cond | 0x6F * B20 | src1.code() * B16 | dst.code() * B12 |
2036 void Assembler::strd(Register src1, Register src2,
2039 DCHECK(!src1.is(lr)); // r14.
2040 DCHECK_EQ(0, src1.code() % 2);
2041 DCHECK_EQ(src1.code() + 1, src2.code());
2043 addrmod3(cond | B7 | B6 | B5 | B4, src1, dst);
2730 const Register src1,
2737 DCHECK(!src1.is(pc) && !src2.is(pc));
2741 src1.code()*B12 | 0xB*B8 | m*B5 | B4 | vm);
3037 const DwVfpRegister src1,
3048 src1.split_code(&vn, &n);
3056 void Assembler::vadd(const SwVfpRegister dst, const SwVfpRegister src1,
3066 src1.split_code(&vn, &n);
3075 const DwVfpRegister src1,
3086 src1.split_code(&vn, &n);
3094 void Assembler::vsub(const SwVfpRegister dst, const SwVfpRegister src1,
3104 src1.split_code(&vn, &n);
3113 const DwVfpRegister src1,
3124 src1.split_code(&vn, &n);
3132 void Assembler::vmul(const SwVfpRegister dst, const SwVfpRegister src1,
3142 src1.split_code(&vn, &n);
3151 const DwVfpRegister src1,
3160 src1.split_code(&vn, &n);
3168 void Assembler::vmla(const SwVfpRegister dst, const SwVfpRegister src1,
3176 src1.split_code(&vn, &n);
3185 const DwVfpRegister src1,
3194 src1.split_code(&vn, &n);
3202 void Assembler::vmls(const SwVfpRegister dst, const SwVfpRegister src1,
3210 src1.split_code(&vn, &n);
3219 const DwVfpRegister src1,
3230 src1.split_code(&vn, &n);
3238 void Assembler::vdiv(const SwVfpRegister dst, const SwVfpRegister src1,
3248 src1.split_code(&vn, &n);
3256 void Assembler::vcmp(const DwVfpRegister src1,
3264 src1.split_code(&vd, &d);
3272 void Assembler::vcmp(const SwVfpRegister src1, const SwVfpRegister src2,
3279 src1.split_code(&vd, &d);
3287 void Assembler::vcmp(const DwVfpRegister src1,
3296 src1.split_code(&vd, &d);
3301 void Assembler::vcmp(const SwVfpRegister src1, const float src2,
3309 src1.split_code(&vd, &d);
