Lines Matching refs:fbits
7685 // value. All possible values of 'fbits' are tested. The expected value is
7735 // Test all possible values of fbits.
7736 for (int fbits = 1; fbits <= 32; fbits++) {
7737 __ Scvtf(d0, x10, fbits);
7738 __ Ucvtf(d1, x10, fbits);
7739 __ Scvtf(d2, w11, fbits);
7740 __ Ucvtf(d3, w11, fbits);
7741 __ Str(d0, MemOperand(x0, fbits * kDRegSize));
7742 __ Str(d1, MemOperand(x1, fbits * kDRegSize));
7743 __ Str(d2, MemOperand(x2, fbits * kDRegSize));
7744 __ Str(d3, MemOperand(x3, fbits * kDRegSize));
7747 // Conversions from W registers can only handle fbits values <= 32, so just
7748 // test conversions from X registers for 32 < fbits <= 64.
7749 for (int fbits = 33; fbits <= 64; fbits++) {
7750 __ Scvtf(d0, x10, fbits);
7751 __ Ucvtf(d1, x10, fbits);
7752 __ Str(d0, MemOperand(x0, fbits * kDRegSize));
7753 __ Str(d1, MemOperand(x1, fbits * kDRegSize));
7763 for (int fbits = 0; fbits <= 32; fbits++) {
7764 double expected_scvtf = expected_scvtf_base / pow(2.0, fbits);
7765 double expected_ucvtf = expected_ucvtf_base / pow(2.0, fbits);
7766 CHECK_EQUAL_FP64(expected_scvtf, results_scvtf_x[fbits]);
7767 CHECK_EQUAL_FP64(expected_ucvtf, results_ucvtf_x[fbits]);
7768 if (cvtf_s32) CHECK_EQUAL_FP64(expected_scvtf, results_scvtf_w[fbits]);
7769 if (cvtf_u32) CHECK_EQUAL_FP64(expected_ucvtf, results_ucvtf_w[fbits]);
7771 for (int fbits = 33; fbits <= 64; fbits++) {
7772 double expected_scvtf = expected_scvtf_base / pow(2.0, fbits);
7773 double expected_ucvtf = expected_ucvtf_base / pow(2.0, fbits);
7774 CHECK_EQUAL_FP64(expected_scvtf, results_scvtf_x[fbits]);
7775 CHECK_EQUAL_FP64(expected_ucvtf, results_ucvtf_x[fbits]);
7890 // Test all possible values of fbits.
7891 for (int fbits = 1; fbits <= 32; fbits++) {
7892 __ Scvtf(s0, x10, fbits);
7893 __ Ucvtf(s1, x10, fbits);
7894 __ Scvtf(s2, w11, fbits);
7895 __ Ucvtf(s3, w11, fbits);
7896 __ Str(s0, MemOperand(x0, fbits * kSRegSize));
7897 __ Str(s1, MemOperand(x1, fbits * kSRegSize));
7898 __ Str(s2, MemOperand(x2, fbits * kSRegSize));
7899 __ Str(s3, MemOperand(x3, fbits * kSRegSize));
7902 // Conversions from W registers can only handle fbits values <= 32, so just
7903 // test conversions from X registers for 32 < fbits <= 64.
7904 for (int fbits = 33; fbits <= 64; fbits++) {
7905 __ Scvtf(s0, x10, fbits);
7906 __ Ucvtf(s1, x10, fbits);
7907 __ Str(s0, MemOperand(x0, fbits * kSRegSize));
7908 __ Str(s1, MemOperand(x1, fbits * kSRegSize));
7918 for (int fbits = 0; fbits <= 32; fbits++) {
7919 float expected_scvtf = expected_scvtf_base / powf(2, fbits);
7920 float expected_ucvtf = expected_ucvtf_base / powf(2, fbits);
7921 CHECK_EQUAL_FP32(expected_scvtf, results_scvtf_x[fbits]);
7922 CHECK_EQUAL_FP32(expected_ucvtf, results_ucvtf_x[fbits]);
7923 if (cvtf_s32) CHECK_EQUAL_FP32(expected_scvtf, results_scvtf_w[fbits]);
7924 if (cvtf_u32) CHECK_EQUAL_FP32(expected_ucvtf, results_ucvtf_w[fbits]);
7927 for (int fbits = 33; fbits <= 64; fbits++) {
7929 float expected_scvtf = expected_scvtf_base / powf(2, fbits);
7930 float expected_ucvtf = expected_ucvtf_base / powf(2, fbits);
7931 CHECK_EQUAL_FP32(expected_scvtf, results_scvtf_x[fbits]);
7932 CHECK_EQUAL_FP32(expected_ucvtf, results_ucvtf_x[fbits]);
