Lines Matching refs:vex_printf
369 vex_printf("amd64toIR: unimplemented feature\n");
375 vex_printf(format, ## args)
626 default: vex_printf("\nszToITy(%d)\n", n);
1770 vex_printf("\nsrc, dst tys are: ");
1772 vex_printf(", ");
1774 vex_printf("\n");
2296 if (0) vex_printf("AbiHint: %s\n", who);
2948 vex_printf("vex amd64->IR: sbb %%r,%%r optimisation(1)\n");
3125 if (0) vex_printf("locked case\n" );
3130 if (0) vex_printf("nonlocked case\n");
3760 vex_printf("%s%c ",
3763 vex_printf("%s", shift_expr_txt);
3766 vex_printf(", %s\n", nameIRegE(sz,pfx,modrm));
3771 vex_printf("%s%c ",
3774 vex_printf("%s", shift_expr_txt);
3777 vex_printf(", %s\n", dis_buf);
5476 vex_printf("unhandled opc_aux = 0x%2x\n",
5478 vex_printf("first_opcode == 0xD8\n");
5736 vex_printf("unhandled opc_aux = 0x%2x\n",
5738 vex_printf("first_opcode == 0xD9\n");
6136 vex_printf("unhandled opc_aux = 0x%2x\n",
6138 vex_printf("first_opcode == 0xDA\n");
6301 vex_printf("unhandled opc_aux = 0x%2x\n",
6303 vex_printf("first_opcode == 0xDB\n");
6451 vex_printf("unhandled opc_aux = 0x%2x\n",
6453 vex_printf("first_opcode == 0xDC\n");
6687 vex_printf("unhandled opc_aux = 0x%2x\n",
6689 vex_printf("first_opcode == 0xDD\n");
6821 vex_printf("unhandled opc_aux = 0x%2x\n",
6823 vex_printf("first_opcode == 0xDE\n");
6938 vex_printf("unhandled opc_aux = 0x%2x\n",
6940 vex_printf("first_opcode == 0xDF\n");
7155 vex_printf("\n0x%x\n", (UInt)opc);
32077 vex_printf("vex amd64->IR: unhandled instruction bytes: "
32087 vex_printf("vex amd64->IR: REX=%d REX.W=%d REX.R=%d REX.X=%d REX.B=%d\n",
32090 vex_printf("vex amd64->IR: VEX=%d VEX.L=%d VEX.nVVVV=0x%x ESC=%s\n",
32097 vex_printf("vex amd64->IR: PFX.66=%d PFX.F2=%d PFX.F3=%d\n",
32195 vex_printf("\n");
32196 vex_printf("assumed next %%rip = 0x%llx\n",
32198 vex_printf(" actual next %%rip = 0x%llx\n",
32221 vex_printf("\t\t");
32223 vex_printf("\n");
