Lines Matching refs:fbits
9389 UInt fbits = 0;
9390 Bool ok = getLaneInfo_IMMH_IMMB(&fbits, &size, immh, immb);
9397 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32));
9398 Double scale = two_to_the_minus(fbits);
9419 ch, dd, ch, nn, fbits);
9427 UInt fbits = 0;
9428 Bool ok = getLaneInfo_IMMH_IMMB(&fbits, &size, immh, immb);
9435 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32));
9436 Double scale = two_to_the_plus(fbits);
9458 ch, dd, ch, nn, fbits);
10744 UInt fbits = 0;
10745 Bool ok = getLaneInfo_IMMH_IMMB(&fbits, &size, immh, immb);
10754 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32));
10755 Double scale = two_to_the_minus(fbits);
10780 nameQReg128(dd), arr, nameQReg128(nn), arr, fbits);
10790 UInt fbits = 0;
10791 Bool ok = getLaneInfo_IMMH_IMMB(&fbits, &size, immh, immb);
10800 vassert(fbits >= 1 && fbits <= (isD ? 64 : 32));
10801 Double scale = two_to_the_plus(fbits);
10827 nameQReg128(dd), arr, nameQReg128(nn), arr, fbits);
13401 /* -------- 0 0 00 11 000: FCVTZS w_s_#fbits -------- */
13402 /* -------- 1 0 01 11 000: FCVTZS w_d_#fbits -------- */
13403 /* -------- 2 1 00 11 000: FCVTZS x_s_#fbits -------- */
13404 /* -------- 3 1 01 11 000: FCVTZS x_d_#fbits -------- */
13406 /* -------- 4 0 00 11 001: FCVTZU w_s_#fbits -------- */
13407 /* -------- 5 0 01 11 001: FCVTZU w_d_#fbits -------- */
13408 /* -------- 6 1 00 11 001: FCVTZU x_s_#fbits -------- */
13409 /* -------- 7 1 01 11 001: FCVTZU x_d_#fbits -------- */
13415 Int fbits = 64 - sc;
13416 vassert(fbits >= 1 && fbits <= (isI64 ? 64 : 32));
13418 Double scale = two_to_the_plus(fbits);
13436 nameQRegLO(nn, isF64 ? Ity_F64 : Ity_F32), fbits);
13441 /* ------ x,0x,00,010 SCVTF s/d, w/x, #fbits ------ */
13442 /* ------ x,0x,00,011 UCVTF s/d, w/x, #fbits ------ */
13444 0 0 0 0 11110 00 0 00 010 scale n d SCVTF Sd, Wn, #fbits
13445 fbits
13446 2 1 0 0 11110 00 0 00 010 scale n d SCVTF Sd, Xn, #fbits
13447 3 1 0 0 11110 01 0 00 010 scale n d SCVTF Dd, Xn, #fbits
13449 4 0 0 0 11110 00 0 00 011 scale n d UCVTF Sd, Wn, #fbits
13450 5 0 0 0 11110 01 0 00 011 scale n d UCVTF Dd, Wn, #fbits
13451 6 1 0 0 11110 00 0 00 011 scale n d UCVTF Sd, Xn, #fbits
13452 7 1 0 0 11110 01 0 00 011 scale n d UCVTF Dd, Xn, #fbits
13466 Int fbits = 64 - sc;
13467 vassert(fbits >= 1 && fbits <= (isI64 ? 64 : 32));
13469 Double scale = two_to_the_minus(fbits);
13487 nameIRegOrZR(isI64, nn), fbits);
