Lines Matching refs:VexGuestMIPS32State
106 ret = offsetof(VexGuestMIPS32State, guest_r0); break;
108 ret = offsetof(VexGuestMIPS32State, guest_r1); break;
110 ret = offsetof(VexGuestMIPS32State, guest_r2); break;
112 ret = offsetof(VexGuestMIPS32State, guest_r3); break;
114 ret = offsetof(VexGuestMIPS32State, guest_r4); break;
116 ret = offsetof(VexGuestMIPS32State, guest_r5); break;
118 ret = offsetof(VexGuestMIPS32State, guest_r6); break;
120 ret = offsetof(VexGuestMIPS32State, guest_r7); break;
122 ret = offsetof(VexGuestMIPS32State, guest_r8); break;
124 ret = offsetof(VexGuestMIPS32State, guest_r9); break;
126 ret = offsetof(VexGuestMIPS32State, guest_r10); break;
128 ret = offsetof(VexGuestMIPS32State, guest_r11); break;
130 ret = offsetof(VexGuestMIPS32State, guest_r12); break;
132 ret = offsetof(VexGuestMIPS32State, guest_r13); break;
134 ret = offsetof(VexGuestMIPS32State, guest_r14); break;
136 ret = offsetof(VexGuestMIPS32State, guest_r15); break;
138 ret = offsetof(VexGuestMIPS32State, guest_r16); break;
140 ret = offsetof(VexGuestMIPS32State, guest_r17); break;
142 ret = offsetof(VexGuestMIPS32State, guest_r18); break;
144 ret = offsetof(VexGuestMIPS32State, guest_r19); break;
146 ret = offsetof(VexGuestMIPS32State, guest_r20); break;
148 ret = offsetof(VexGuestMIPS32State, guest_r21); break;
150 ret = offsetof(VexGuestMIPS32State, guest_r22); break;
152 ret = offsetof(VexGuestMIPS32State, guest_r23); break;
154 ret = offsetof(VexGuestMIPS32State, guest_r24); break;
156 ret = offsetof(VexGuestMIPS32State, guest_r25); break;
158 ret = offsetof(VexGuestMIPS32State, guest_r26); break;
160 ret = offsetof(VexGuestMIPS32State, guest_r27); break;
162 ret = offsetof(VexGuestMIPS32State, guest_r28); break;
164 ret = offsetof(VexGuestMIPS32State, guest_r29); break;
166 ret = offsetof(VexGuestMIPS32State, guest_r30); break;
168 ret = offsetof(VexGuestMIPS32State, guest_r31); break;
247 #define OFFB_PC offsetof(VexGuestMIPS32State, guest_PC)
261 ret = offsetof(VexGuestMIPS32State, guest_f0); break;
263 ret = offsetof(VexGuestMIPS32State, guest_f1); break;
265 ret = offsetof(VexGuestMIPS32State, guest_f2); break;
267 ret = offsetof(VexGuestMIPS32State, guest_f3); break;
269 ret = offsetof(VexGuestMIPS32State, guest_f4); break;
271 ret = offsetof(VexGuestMIPS32State, guest_f5); break;
273 ret = offsetof(VexGuestMIPS32State, guest_f6); break;
275 ret = offsetof(VexGuestMIPS32State, guest_f7); break;
277 ret = offsetof(VexGuestMIPS32State, guest_f8); break;
279 ret = offsetof(VexGuestMIPS32State, guest_f9); break;
281 ret = offsetof(VexGuestMIPS32State, guest_f10); break;
283 ret = offsetof(VexGuestMIPS32State, guest_f11); break;
285 ret = offsetof(VexGuestMIPS32State, guest_f12); break;
287 ret = offsetof(VexGuestMIPS32State, guest_f13); break;
289 ret = offsetof(VexGuestMIPS32State, guest_f14); break;
291 ret = offsetof(VexGuestMIPS32State, guest_f15); break;
293 ret = offsetof(VexGuestMIPS32State, guest_f16); break;
295 ret = offsetof(VexGuestMIPS32State, guest_f17); break;
297 ret = offsetof(VexGuestMIPS32State, guest_f18); break;
299 ret = offsetof(VexGuestMIPS32State, guest_f19); break;
301 ret = offsetof(VexGuestMIPS32State, guest_f20); break;
303 ret = offsetof(VexGuestMIPS32State, guest_f21); break;
305 ret = offsetof(VexGuestMIPS32State, guest_f22); break;
307 ret = offsetof(VexGuestMIPS32State, guest_f23); break;
309 ret = offsetof(VexGuestMIPS32State, guest_f24); break;
311 ret = offsetof(VexGuestMIPS32State, guest_f25); break;
313 ret = offsetof(VexGuestMIPS32State, guest_f26); break;
315 ret = offsetof(VexGuestMIPS32State, guest_f27); break;
317 ret = offsetof(VexGuestMIPS32State, guest_f28); break;
319 ret = offsetof(VexGuestMIPS32State, guest_f29); break;
321 ret = offsetof(VexGuestMIPS32State, guest_f30); break;
323 ret = offsetof(VexGuestMIPS32State, guest_f31); break;
410 ret = offsetof(VexGuestMIPS32State, guest_ac0); break;
412 ret = offsetof(VexGuestMIPS32State, guest_ac1); break;
414 ret = offsetof(VexGuestMIPS32State, guest_ac2); break;
416 ret = offsetof(VexGuestMIPS32State, guest_ac3); break;
1036 return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_DSPControl), Ity_I32);
1046 stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_DSPControl), e));
1071 return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_HI), Ity_I32);
1079 return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_LO), Ity_I32);
1087 return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_FCSR), Ity_I32);
1109 stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_FCSR), e));
1152 d->fxState[0].offset = offsetof(VexGuestMIPS32State, guest_FCSR);
1175 d->fxState[0].offset = offsetof(VexGuestMIPS32State, guest_FCSR);
1204 return IRExpr_Get(offsetof(VexGuestMIPS32State, guest_ULR), Ity_I32);
1227 stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_LO), e));
1245 stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_HI), e));
1504 assign(rm_MIPS, binop(Iop_And32, IRExpr_Get(offsetof(VexGuestMIPS32State,
12127 putIReg(11, IRExpr_Get(offsetof(VexGuestMIPS32State,
12157 stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_CMSTART),
12159 stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_CMLEN),
12922 IRExpr_Get(offsetof(VexGuestMIPS32State,
17192 stmt(IRStmt_Put(offsetof(VexGuestMIPS32State, guest_PC),
