Lines Matching refs:fs
1112 /* fs - fpu source register number.
1118 static void calculateFCSR(UInt fs, UInt ft, UInt inst, Bool sz32, UInt opN)
1128 mkU32(fs),
1136 mkU32(fs),
1155 d->fxState[1].offset = floatGuestRegOffset(fs);
1160 d->fxState[2].offset = floatGuestRegOffset(fs+1);
1178 d->fxState[1].offset = floatGuestRegOffset(fs);
1186 d->fxState[3].offset = floatGuestRegOffset(fs+1);
1740 UInt fs = get_fs(cins);
1748 DIP("c.%s.s %u, f%u, f%u", showCondCode(cond), fpc_cc, fs, ft);
1759 getFReg(fs))));
1862 assign(ccIR, binop(Iop_CmpF64, unop(Iop_F32toF64, getFReg(fs)),
1957 DIP("c.%s.d %u, f%u, f%u", showCondCode(cond), fpc_cc, fs, ft);
1962 assign(ccIR, binop(Iop_CmpF64, getDReg(fs), getDReg(ft)));
12034 UInt opcode, cins, rs, rt, rd, sa, ft, fs, fd, fmt, tf, nd, function,
12184 fs = get_fs(cins);
12230 DIP("mfhc1 r%u, f%u", rt, fs);
12234 assign(t0, unop(Iop_ReinterpF64asI64, getDReg(fs)));
12242 DIP("mthc1 r%u, f%u", rt, fs);
12248 getDReg(fs)))));
12249 putDReg(fs, unop(Iop_ReinterpI64asF64, mkexpr(t0)));
12302 getLoFromF64(tyF, getFReg(fs)))));
12307 putDReg(fd, binop(Iop_SqrtF64, rm, getDReg(fs)));
12318 DIP("abs.s f%u, f%u", fd, fs);
12320 getLoFromF64(tyF, getFReg(fs)))));
12323 DIP("abs.d f%u, f%u", fd, fs);
12324 putDReg(fd, unop(Iop_AbsF64, getDReg(fs)));
12334 DIP("mul.d f%u, f%u, f%u", fd, fs, ft);
12336 putDReg(fd, triop(Iop_MulF64, rm, getDReg(fs),
12341 DIP("mul.s f%u, f%u, f%u", fd, fs, ft);
12344 getLoFromF64(tyF, getFReg(fs)),
12356 DIP("div.d f%u, f%u, f%u", fd, fs, ft);
12358 putDReg(fd, triop(Iop_DivF64, rm, getDReg(fs),
12363 DIP("div.s f%u, f%u, f%u", fd, fs, ft);
12364 calculateFCSR(fs, ft, DIVS, False, 2);
12367 getLoFromF64(tyF, getFReg(fs)),
12379 DIP("sub.d f%u, f%u, f%u", fd, fs, ft);
12380 calculateFCSR(fs, ft, SUBD, False, 2);
12382 putDReg(fd, triop(Iop_SubF64, rm, getDReg(fs),
12387 DIP("sub.s f%u, f%u, f%u", fd, fs, ft);
12388 calculateFCSR(fs, ft, SUBS, True, 2);
12391 getLoFromF64(tyF, getFReg(fs)),
12403 DIP("mov.d f%u, f%u", fd, fs);
12405 putDReg(fd, getDReg(fs));
12407 putFReg(fd, getFReg(fs));
12408 putFReg(fd + 1, getFReg(fs + 1));
12412 DIP("mov.s f%u, f%u", fd, fs);
12413 putFReg(fd, getFReg(fs));
12423 DIP("neg.s f%u, f%u", fd, fs);
12425 getLoFromF64(tyF, getFReg(fs)))));
12428 DIP("neg.d f%u, f%u", fd, fs);
12429 putDReg(fd, unop(Iop_NegF64, getDReg(fs)));
12439 DIP("round.l.s f%u, f%u", fd, fs);
12441 calculateFCSR(fs, 0, ROUNDLS, True, 1);
12445 getLoFromF64(Ity_F64, getFReg(fs))));
12453 DIP("round.l.d f%u, f%u", fd, fs);
12455 calculateFCSR(fs, 0, ROUNDLD, False, 1);
12457 getDReg(fs)));
12471 DIP("trunc.l.s f%u, f%u", fd, fs);
12473 calculateFCSR(fs, 0, TRUNCLS, True, 1);
12476 getLoFromF64(Ity_F64, getFReg(fs))));
12484 DIP("trunc.l.d f%u, f%u", fd, fs);
12486 calculateFCSR(fs, 0, TRUNCLD, False, 1);
12488 getDReg(fs)));
12501 DIP("recip.s f%u, f%u", fd, fs);
12506 getFReg(fs)))));
12510 DIP("recip.d f%u, f%u", fd, fs);
12512 /* putDReg(fd, 1.0/getDreg(fs)); */
12515 mkU64(ONE_DOUBLE)), getDReg(fs)));
12527 DIP("movn.s f%u, f%u, r%u", fd, fs, rt);
12533 assign(t1, getFReg(fs));
12538 assign(t1, getFReg(fs));
12542 assign(t1, unop(Iop_F32toF64, getFReg(fs)));
12566 DIP("movn.d f%u, f%u, r%u", fd, fs, rt);
12576 putDReg(fd, IRExpr_ITE(mkexpr(t3), getDReg(fs), getDReg(fd)));
12586 DIP("movz.s f%u, f%u, r%u", fd, fs, rt);
12593 assign(t1, getFReg(fs));
12600 assign(t1, unop(Iop_F32toF64, getFReg(fs)));
12623 DIP("movz.d f%u, f%u, r%u", fd, fs, rt);
12631 putDReg(fd, IRExpr_ITE(mkexpr(t3), getDReg(fs), getDReg(fd)));
12643 DIP("movt.d f%u, f%u, %u", fd, fs, mov_cc);
12663 getDReg(fs), getDReg(fd)));
12667 DIP("movt.s f%u, f%u, %u", fd, fs, mov_cc);
12677 assign(t5, getFReg(fs));
12680 assign(t5, unop(Iop_F32toF64, getFReg(fs)));
12724 DIP("movf.d f%u, f%u, %u", fd, fs, mov_cc);
12744 getDReg(fs), getDReg(fd)));
12748 DIP("movf.s f%u, f%u, %u", fd, fs, mov_cc);
12757 assign(t5, getFReg(fs));
12760 assign(t5, unop(Iop_F32toF64, getFReg(fs)));
12806 DIP("add.s f%u, f%u, f%u", fd, fs, ft);
12807 calculateFCSR(fs, ft, ADDS, True, 2);
12810 getLoFromF64(tyF, getFReg(fs)),
12815 DIP("add.d f%u, f%u, f%u", fd, fs, ft);
12816 calculateFCSR(fs, ft, ADDD, False, 2);
12818 putDReg(fd, triop(Iop_AddF64, rm, getDReg(fs), getDReg(ft)));
12823 DIP("mtc1 r%u, f%u", rt, fs);
12830 putFReg(fs, mkWidenFromF32(tyF, mkexpr(t1)));
12832 putFReg(fs, unop(Iop_ReinterpI32asF32, getIReg(rt)));
12836 DIP("dmtc1 r%u, f%u", rt, fs);
12838 putFReg(fs, unop(Iop_ReinterpI64asF64, getIReg(rt)));
12842 DIP("mfc1 r%u, f%u", rt, fs);
12846 assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
12850 putIReg(rt, unop(Iop_ReinterpF32asI32, getFReg(fs)));
12855 DIP("dmfc1 r%u, f%u", rt, fs);
12856 putIReg(rt, unop(Iop_ReinterpF64asI64, getFReg(fs)));
12860 DIP("ctc1 r%u, f%u", rt, fs);
12869 if (fs == 25) { /* FCCR */
12881 } else if (fs == 26) { /* FEXR */
12892 } else if (fs == 28) {
12906 } else if (fs == 31) {
12911 DIP("cfc1 r%u, f%u", rt, fs);
12920 if (fs == 0) {
12926 } else if (fs == 25) {
12935 } else if (fs == 26) {
12944 } else if (fs == 28) {
12953 } else if (fs == 31) {
12965 DIP("cvt.d.s f%u, f%u", fd, fs);
12966 calculateFCSR(fs, 0, CVTDS, True, 1);
12973 assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
12981 putDReg(fd, unop(Iop_F32toF64, getFReg(fs)));
12985 DIP("cvt.d.w %u, %u", fd, fs);
12986 calculateFCSR(fs, 0, CVTDW, True, 1);
12993 assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
13000 assign(t0, unop(Iop_ReinterpF32asI32, getFReg(fs)));
13007 DIP("cvt.d.l %u, %u", fd, fs);
13008 calculateFCSR(fs, 0, CVTDL, False, 1);
13010 assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
13026 DIP("cvt.s.w %u, %u", fd, fs);
13027 calculateFCSR(fs, 0, CVTSW, True, 1);
13034 assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
13041 assign(t0, unop(Iop_ReinterpF32asI32, getFReg(fs)));
13048 DIP("cvt.s.d %u, %u", fd, fs);
13049 calculateFCSR(fs, 0, CVTSD, False, 1);
13052 getDReg(fs)));
13057 DIP("cvt.s.l %u, %u", fd, fs);
13058 calculateFCSR(fs, 0, CVTSL, False, 1);
13060 assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
13074 DIP("cvt.w.s %u, %u", fd, fs);
13075 calculateFCSR(fs, 0, CVTWS, True, 1);
13080 getLoFromF64(tyF, getFReg(fs))))
13085 DIP("cvt.w.d %u, %u", fd, fs);
13086 calculateFCSR(fs, 0, CVTWD, False, 1);
13090 getDReg(fs)));
13104 DIP("cvt.l.s %u, %u", fd, fs);
13106 calculateFCSR(fs, 0, CVTLS, True, 1);
13110 getLoFromF64(tyF, getFReg(fs))));
13119 DIP("cvt.l.d %u, %u", fd, fs);
13121 calculateFCSR(fs, 0, CVTLD, False, 1);
13123 get_IR_roundingmode(), getDReg(fs)));
13138 DIP("floor.l.s %u, %u", fd, fs);
13140 calculateFCSR(fs, 0, FLOORLS, True, 1);
13144 getLoFromF64(tyF, getFReg(fs))));
13153 DIP("floor.l.d %u, %u", fd, fs);
13155 calculateFCSR(fs, 0, FLOORLD, False, 1);
13157 getDReg(fs)));
13170 DIP("round.w.s f%u, f%u", fd, fs);
13171 calculateFCSR(fs, 0, ROUNDWS, True, 1);
13178 assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
13190 getFReg(fs)));
13194 DIP("round.w.d f%u, f%u", fd, fs);
13195 calculateFCSR(fs, 0, ROUNDWD, False, 1);
13199 getDReg(fs)));
13206 getDReg(fs)));
13220 DIP("floor.w.s f%u, f%u", fd, fs);
13221 calculateFCSR(fs, 0, FLOORWS, True, 1);
13228 assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
13240 getFReg(fs)));
13244 DIP("floor.w.d f%u, f%u", fd, fs);
13245 calculateFCSR(fs, 0, FLOORWD, False, 1);
13249 getDReg(fs)));
13257 getDReg(fs)));
13271 DIP("trunc.w.s %u, %u", fd, fs);
13272 calculateFCSR(fs, 0, TRUNCWS, True, 1);
13279 assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
13291 getFReg(fs)));
13294 DIP("trunc.w.d %u, %u", fd, fs);
13295 calculateFCSR(fs, 0, TRUNCWD, False, 1);
13300 getFReg(fs)));
13308 getDReg(fs)));
13322 DIP("ceil.w.s %u, %u", fd, fs);
13323 calculateFCSR(fs, 0, CEILWS, True, 1);
13330 assign(t0, unop(Iop_ReinterpF64asI64, getFReg(fs)));
13342 getFReg(fs)));
13346 DIP("ceil.w.d %u, %u", fd, fs);
13347 calculateFCSR(fs, 0, CEILWD, False, 1);
13351 getDReg(fs)));
13356 getDReg(fs)));
13370 DIP("ceil.l.s %u, %u", fd, fs);
13372 calculateFCSR(fs, 0, CEILLS, True, 1);
13376 getLoFromF64(tyF, getFReg(fs))));
13385 DIP("ceil.l.d %u, %u", fd, fs);
13387 calculateFCSR(fs, 0, CEILLD, False, 1);
13389 getDReg(fs)));
13404 DIP("rsqrt.s %u, %u", fd, fs);
13409 getFReg(fs))))));
13413 DIP("rsqrt.d %u, %u", fd, fs);
13418 binop(Iop_SqrtF64, rm, getDReg(fs))));
13652 store(mkexpr(t0), getLoFromF64(tyF, getFReg(fs)));
13658 store(mkexpr(t0), getFReg(fs));
13668 store(mkexpr(t0), getFReg(fs));
13677 store(mkexpr(t0), getFReg(fs));
13678 store(mkexpr(t1), getFReg(fs + 1));
13680 store(mkexpr(t0), getFReg(fs + 1));
13681 store(mkexpr(t1), getFReg(fs));
13693 store(mkexpr(t1), getFReg(fs));
13701 DIP("madd.s f%u, f%u, f%u, f%u", fd, fmt, fs, ft);
13706 getLoFromF64(tyF, getFReg(fs)),
13712 DIP("madd.d f%u, f%u, f%u, f%u", fd, fmt, fs, ft);
13714 putDReg(fd, qop(Iop_MAddF64, rm, getDReg(fmt), getDReg(fs),
13719 DIP("msub.s f%u, f%u, f%u, f%u", fd, fmt, fs, ft);
13724 getLoFromF64(tyF, getFReg(fs)),
13730 DIP("msub.d f%u, f%u, f%u, f%u", fd, fmt, fs, ft);
13732 putDReg(fd, qop(Iop_MSubF64, rm, getDReg(fmt), getDReg(fs),
13737 DIP("nmadd.s f%u, f%u, f%u, f%u", fd, fmt, fs, ft);
13742 getLoFromF64(tyF, getFReg(fs)),
13749 DIP("nmadd.d f%u, f%u, f%u, f%u", fd, fmt, fs, ft);
13752 assign(t1, qop(Iop_MAddF64, rm, getDReg(fmt), getDReg(fs),
13758 DIP("nmsub.s f%u, f%u, f%u, f%u", fd, fmt, fs, ft);
13763 getLoFromF64(tyF, getFReg(fs)),
13770 DIP("nmsub.d f%u, f%u, f%u, f%u", fd, fmt, fs, ft);
13773 assign(t1, qop(Iop_MSubF64, rm, getDReg(fmt), getDReg(fs),
