Lines Matching defs:x9
85 // X9 is a chaining/spill temporary, not available to regalloc.
116 // x9 is used as a spill/reload/chaining/call temporary
1474 vex_printf("imm64 x9,0x%llx; ", i->ARM64in.XDirect.dstGA);
1475 vex_printf("str x9,");
1477 vex_printf("; imm64-exactly4 x9,$disp_cp_chain_me_to_%sEP; ",
1479 vex_printf("blr x9 }");
1489 vex_printf("; imm64 x9,$disp_cp_xindir; ");
1490 vex_printf("br x9 }");
1502 vex_printf("imm64 x9,$disp_cp_xassisted; ");
1503 vex_printf("br x9 }");
1886 vex_printf("; bpl nofail; ldr x9,");
1888 vex_printf("; br x9; nofail:");
1891 vex_printf("(profInc) imm64-fixed4 x9,$NotKnownYet; "
1892 "ldr x8,[x9]; add x8,x8,#1, str x8,[x9]");
2032 loaded into a register. However, we reserve x9 for that
2033 purpose so there's no further complexity here. Stating x9
2469 /* hardwires x8 and x9 -- nothing to modify. */
2532 HReg x9 = hregARM64_X9(); // spill temporary
2535 *i1 = ARM64Instr_Arith(x9, x21, ARM64RIA_I12(offsetB, 0), True);
2536 *i2 = ARM64Instr_VLdStQ(False/*!isLoad*/, rreg, x9);
2573 HReg x9 = hregARM64_X9(); // spill temporary
2576 *i1 = ARM64Instr_Arith(x9, x21, ARM64RIA_I12(offsetB, 0), True);
2577 *i2 = ARM64Instr_VLdStQ(True/*isLoad*/, rreg, x9);
3515 /* imm64 x9, dstGA */
3516 /* str x9, amPC */
3526 /* movw x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[15:0] */
3527 /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[31:15], lsl 16 */
3528 /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[47:32], lsl 32 */
3529 /* movk x9, VG_(disp_cp_chain_me_to_{slowEP,fastEP})[63:48], lsl 48 */
3530 /* blr x9 */
3575 /* imm64 x9, VG_(disp_cp_xindir) */
3576 /* br x9 */
3578 *p++ = 0xD61F0120; /* br x9 */
3642 /* imm64 x9, VG_(disp_cp_xassisted) */
3643 /* br x9 */
3645 *p++ = 0xD61F0120; /* br x9 */
3673 /* We'll use x9 as a scratch register to put the target
3695 // x9 = &target
3697 // blr x9
5344 ldr x9, [x21 + #0] 0 == offsetof(host_EvC_FAILADDR)
5345 br x9
5357 *p++ = 0xD61F0120; /* br x9 */
5371 imm64-exactly4 x9, 0x6555'7555'8555'9566
5372 ldr x8, [x9]
5374 str x8, [x9]
5421 movw x9, disp_cp_chain_me_to_EXPECTED[15:0]
5422 movk x9, disp_cp_chain_me_to_EXPECTED[31:15], lsl 16
5423 movk x9, disp_cp_chain_me_to_EXPECTED[47:32], lsl 32
5424 movk x9, disp_cp_chain_me_to_EXPECTED[63:48], lsl 48
5425 blr x9
5437 movw x9, place_to_jump_to[15:0]
5438 movk x9, place_to_jump_to[31:15], lsl 16
5439 movk x9, place_to_jump_to[47:32], lsl 32
5440 movk x9, place_to_jump_to[63:48], lsl 48
5441 br x9
5466 movw x9, place_to_jump_to_EXPECTED[15:0]
5467 movk x9, place_to_jump_to_EXPECTED[31:15], lsl 16
5468 movk x9, place_to_jump_to_EXPECTED[47:32], lsl 32
5469 movk x9, place_to_jump_to_EXPECTED[63:48], lsl 48
5470 br x9
5482 movw x9, disp_cp_chain_me_to[15:0]
5483 movk x9, disp_cp_chain_me_to[31:15], lsl 16
5484 movk x9, disp_cp_chain_me_to[47:32], lsl 32
5485 movk x9, disp_cp_chain_me_to[63:48], lsl 48
5486 blr x9
