Lines Matching full:regn
80 var i, opc, regd, regm, regn, cpsr uint32
192 // load/store regn is cpureg, regm is 8bit offset
194 regn = i >> 16 & 0xf
199 uaddr := uintptr(regs[regn] + regm)
215 uaddr := uintptr(regs[regn] + regm)
232 uaddr := uintptr(regs[regn] + regm)
248 uaddr := uintptr(regs[regn] + regm)
265 // regd, regm, regn are 4bit variables
269 m.freglo[regd] = m.freglo[regm] ^ m.freglo[regn]
270 m.freghi[regd] = m.freghi[regm] ^ m.freghi[regn]
277 case 0xeeb00b00: // D[regd] = const(regn,regm)
278 regn = regn<<4 | regm
280 if regn&0x80 != 0 {
283 if regn&0x40 != 0 {
286 regm |= regn & 0x3f << 16
295 case 0xeeb00a00: // F[regd] = const(regn,regm)
296 regn = regn<<4 | regm
298 if regn&0x80 != 0 {
301 if regn&0x40 != 0 {
304 regm |= regn & 0x3f << 19
312 case 0xee300b00: // D[regd] = D[regn]+D[regm]
313 fputd(regd, fadd64(fgetd(regn), fgetd(regm)))
316 print("*** add D[", regd, "] = D[", regn, "]+D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
320 case 0xee300a00: // F[regd] = F[regn]+F[regm]
321 m.freglo[regd] = f64to32(fadd64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
324 print("*** add F[", regd, "] = F[", regn, "]+F[", regm, "] ", hex(m.freglo[regd]), "\n")
328 case 0xee300b40: // D[regd] = D[regn]-D[regm]
329 fputd(regd, fsub64(fgetd(regn), fgetd(regm)))
332 print("*** sub D[", regd, "] = D[", regn, "]-D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
336 case 0xee300a40: // F[regd] = F[regn]-F[regm]
337 m.freglo[regd] = f64to32(fsub64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
340 print("*** sub F[", regd, "] = F[", regn, "]-F[", regm, "] ", hex(m.freglo[regd]), "\n")
344 case 0xee200b00: // D[regd] = D[regn]*D[regm]
345 fputd(regd, fmul64(fgetd(regn), fgetd(regm)))
348 print("*** mul D[", regd, "] = D[", regn, "]*D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
352 case 0xee200a00: // F[regd] = F[regn]*F[regm]
353 m.freglo[regd] = f64to32(fmul64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
356 print("*** mul F[", regd, "] = F[", regn, "]*F[", regm, "] ", hex(m.freglo[regd]), "\n")
360 case 0xee800b00: // D[regd] = D[regn]/D[regm]
361 fputd(regd, fdiv64(fgetd(regn), fgetd(regm)))
364 print("*** div D[", regd, "] = D[", regn, "]/D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
368 case 0xee800a00: // F[regd] = F[regn]/F[regm]
369 m.freglo[regd] = f64to32(fdiv64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
372 print("*** div F[", regd, "] = F[", regn, "]/F[", regm, "] ", hex(m.freglo[regd]), "\n")
376 case 0xee000b10: // S[regn] = R[regd] (MOVW) (regm ignored)
377 m.freglo[regn] = regs[regd]
380 print("*** cpy S[", regn, "] = R[", regd, "] ", hex(m.freglo[regn]), "\n")
384 case 0xee100b10: // R[regd] = S[regn] (MOVW) (regm ignored)
385 regs[regd] = m.freglo[regn]
388 print("*** cpy R[", regd, "] = S[", regn, "] ", hex(regs[regd]), "\n")
