Lines Matching full:regd
80 var i, opc, regd, regm, regn, cpsr uint32
193 regd = i >> 12 & 0xf
207 m.freglo[regd] = addr[0]
210 print("*** load F[", regd, "] = ", hex(m.freglo[regd]), "\n")
223 m.freglo[regd] = addr[0]
224 m.freghi[regd] = addr[1]
227 print("*** load D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
240 addr[0] = m.freglo[regd]
256 addr[0] = m.freglo[regd]
257 addr[1] = m.freghi[regd]
265 // regd, regm, regn are 4bit variables
269 m.freglo[regd] = m.freglo[regm] ^ m.freglo[regn]
270 m.freghi[regd] = m.freghi[regm] ^ m.freghi[regn]
273 print("*** veor D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
277 case 0xeeb00b00: // D[regd] = const(regn,regm)
287 m.freglo[regd] = 0
288 m.freghi[regd] = regm
291 print("*** immed D[", regd, "] = ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
295 case 0xeeb00a00: // F[regd] = const(regn,regm)
305 m.freglo[regd] = regm
308 print("*** immed D[", regd, "] = ", hex(m.freglo[regd]), "\n")
312 case 0xee300b00: // D[regd] = D[regn]+D[regm]
313 fputd(regd, fadd64(fgetd(regn), fgetd(regm)))
316 print("*** add D[", regd, "] = D[", regn, "]+D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
320 case 0xee300a00: // F[regd] = F[regn]+F[regm]
321 m.freglo[regd] = f64to32(fadd64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
324 print("*** add F[", regd, "] = F[", regn, "]+F[", regm, "] ", hex(m.freglo[regd]), "\n")
328 case 0xee300b40: // D[regd] = D[regn]-D[regm]
329 fputd(regd, fsub64(fgetd(regn), fgetd(regm)))
332 print("*** sub D[", regd, "] = D[", regn, "]-D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
336 case 0xee300a40: // F[regd] = F[regn]-F[regm]
337 m.freglo[regd] = f64to32(fsub64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
340 print("*** sub F[", regd, "] = F[", regn, "]-F[", regm, "] ", hex(m.freglo[regd]), "\n")
344 case 0xee200b00: // D[regd] = D[regn]*D[regm]
345 fputd(regd, fmul64(fgetd(regn), fgetd(regm)))
348 print("*** mul D[", regd, "] = D[", regn, "]*D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
352 case 0xee200a00: // F[regd] = F[regn]*F[regm]
353 m.freglo[regd] = f64to32(fmul64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
356 print("*** mul F[", regd, "] = F[", regn, "]*F[", regm, "] ", hex(m.freglo[regd]), "\n")
360 case 0xee800b00: // D[regd] = D[regn]/D[regm]
361 fputd(regd, fdiv64(fgetd(regn), fgetd(regm)))
364 print("*** div D[", regd, "] = D[", regn, "]/D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
368 case 0xee800a00: // F[regd] = F[regn]/F[regm]
369 m.freglo[regd] = f64to32(fdiv64(f32to64(m.freglo[regn]), f32to64(m.freglo[regm])))
372 print("*** div F[", regd, "] = F[", regn, "]/F[", regm, "] ", hex(m.freglo[regd]), "\n")
376 case 0xee000b10: // S[regn] = R[regd] (MOVW) (regm ignored)
377 m.freglo[regn] = regs[regd]
380 print("*** cpy S[", regn, "] = R[", regd, "] ", hex(m.freglo[regn]), "\n")
384 case 0xee100b10: // R[regd] = S[regn] (MOVW) (regm ignored)
385 regs[regd] = m.freglo[regn]
388 print("*** cpy R[", regd, "] = S[", regn, "] ", hex(regs[regd]), "\n")
393 // regd, regm are 4bit variables
395 case 0xeeb00a40: // F[regd] = F[regm] (MOVF)
396 m.freglo[regd] = m.freglo[regm]
399 print("*** F[", regd, "] = F[", regm, "] ", hex(m.freglo[regd]), "\n")
403 case 0xeeb00b40: // D[regd] = D[regm] (MOVD)
404 m.freglo[regd] = m.freglo[regm]
405 m.freghi[regd] = m.freghi[regm]
408 print("*** D[", regd, "] = D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
412 case 0xeeb10bc0: // D[regd] = sqrt D[regm]
413 fputd(regd, sqrt(fgetd(regm)))
416 print("*** D[", regd, "] = sqrt D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
420 case 0xeeb00bc0: // D[regd] = abs D[regm]
421 m.freglo[regd] = m.freglo[regm]
422 m.freghi[regd] = m.freghi[regm] & (1<<31 - 1)
425 print("*** D[", regd, "] = abs D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
429 case 0xeeb00ac0: // F[regd] = abs F[regm]
430 m.freglo[regd] = m.freglo[regm] & (1<<31 - 1)
433 print("*** F[", regd, "] = abs F[", regm, "] ", hex(m.freglo[regd]), "\n")
437 case 0xeeb40bc0: // D[regd] :: D[regm] (CMPD)
438 cmp, nan := fcmp64(fgetd(regd), fgetd(regm))
442 print("*** cmp D[", regd, "]::D[", regm, "] ", hex(m.fflag), "\n")
446 case 0xeeb40ac0: // F[regd] :: F[regm] (CMPF)
447 cmp, nan := fcmp64(f32to64(m.freglo[regd]), f32to64(m.freglo[regm]))
451 print("*** cmp F[", regd, "]::F[", regm, "] ", hex(m.fflag), "\n")
455 case 0xeeb70ac0: // D[regd] = F[regm] (MOVFD)
456 fputd(regd, f32to64(m.freglo[regm]))
459 print("*** f2d D[", regd, "]=F[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
463 case 0xeeb70bc0: // F[regd] = D[regm] (MOVDF)
464 m.freglo[regd] = f64to32(fgetd(regm))
467 print("*** d2f F[", regd, "]=D[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
471 case 0xeebd0ac0: // S[regd] = F[regm] (MOVFW)
476 m.freglo[regd] = uint32(sval)
478 print("*** fix S[", regd, "]=F[", regm, "] ", hex(m.freglo[regd]), "\n")
482 case 0xeebc0ac0: // S[regd] = F[regm] (MOVFW.U)
487 m.freglo[regd] = uint32(sval)
490 print("*** fix unsigned S[", regd, "]=F[", regm, "] ", hex(m.freglo[regd]), "\n")
494 case 0xeebd0bc0: // S[regd] = D[regm] (MOVDW)
499 m.freglo[regd] = uint32(sval)
502 print("*** fix S[", regd, "]=D[", regm, "] ", hex(m.freglo[regd]), "\n")
506 case 0xeebc0bc0: // S[regd] = D[regm] (MOVDW.U)
511 m.freglo[regd] = uint32(sval)
514 print("*** fix unsigned S[", regd, "]=D[", regm, "] ", hex(m.freglo[regd]), "\n")
518 case 0xeeb80ac0: // D[regd] = S[regm] (MOVWF)
521 fputf(regd, f64to32(fintto64(int64(-cmp))))
522 m.freglo[regd] ^= 0x80000000
524 fputf(regd, f64to32(fintto64(int64(cmp))))
528 print("*** float D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
532 case 0xeeb80a40: // D[regd] = S[regm] (MOVWF.U)
533 fputf(regd, f64to32(fintto64(int64(m.freglo[regm]))))
536 print("*** float unsigned D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
540 case 0xeeb80bc0: // D[regd] = S[regm] (MOVWD)
543 fputd(regd, fintto64(int64(-cmp)))
544 m.freghi[regd] ^= 0x80000000
546 fputd(regd, fintto64(int64(cmp)))
550 print("*** float D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
554 case 0xeeb80b40: // D[regd] = S[regm] (MOVWD.U)
555 fputd(regd, fintto64(int64(m.freglo[regm])))
558 print("*** float unsigned D[", regd, "]=S[", regm, "] ", hex(m.freghi[regd]), "-", hex(m.freglo[regd]), "\n")
