Lines Matching defs:bit
414 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
479 /* The bit that distinguishes CPSR and SPSR. */
945 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1357 /* Errors may be set multiple times during parsing or bit encoding
1403 a 4-bit integer. */
1938 The register stride (minus one) is put in bit 4 of the return value.
2921 /* XXX Now we come to the Thumb specific bit of code. */
3270 and split it into two 4-byte entries, because on 32-bit
3579 /* Emit an expression containing a 32-bit thumb instruction.
4777 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4793 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4795 32-bit X_add_number, though. */
4975 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5847 char *bit;
5849 for (bit = start; bit != p; bit++)
5851 switch (TOLOWER (*bit))
5878 inst.error = _("unexpected bit specified after APSR");
6795 /* There's a possibility of getting a 64-bit immediate here, so
7267 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
7720 /* Don't allow MVN with 8-bit immediate. */
7935 bit positions for register arguments in ARM format instructions. */
8111 constraint (msb > 32, _("bit-field extends past end of register"));
8130 constraint (msb > 32, _("bit-field extends past end of register"));
8143 _("bit-field extends past end of register"));
8151 BKPT <16 bit unsigned immediate>
8153 The bit pattern given in insns[] has the COND_ALWAYS condition,
8752 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9098 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9304 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9307 before extracting the 16-bit value.
9885 Bit 4 should be 0. */
10047 /* Table of Thumb instructions which exist in both 16- and 32-bit
10050 possible 16-bit encoding for the instruction, this table always
10135 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10136 as 16-bit instructions. */
10285 /* See if we can do this with a 16-bit instruction. */
10404 /* Generate a 32-bit opcode. */
10412 /* Generate a 16-bit opcode. */
10422 /* Arithmetic instructions for which there is just one 16-bit
10448 /* For an immediate, we always generate a 32-bit opcode;
10460 /* See if we can do this with a 16-bit instruction. */
10513 the destination operand in a 16-bit instruction. For instance, all
10536 /* For an immediate, we always generate a 32-bit opcode;
10548 /* See if we can do this with a 16-bit instruction. */
10617 constraint (msb > 32, _("bit-field extends past end of register"));
10648 constraint (msb > 32, _("bit
10670 _("bit-field extends past end of register"));
11081 /* See if we can use a 16-bit instruction. */
11114 case 1 and 2 which can be converted into a 16-bit
11256 /* Insn may have a 16-bit form. */
11304 /* Definitely a 32-bit variant. */
11852 /* For an immediate, we always generate a 32-bit opcode;
11862 /* See if we can do this with a 16-bit instruction. */
12025 /* 16-bit MULS/Conditional MUL. */
12040 /* 32-bit MUL. */
12365 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12636 inst.instruction |= 0x00200000; /* sh bit. */
13118 /* Bit masks used in type checking given instructions.
13120 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13275 means the Q bit should be set). */
13402 handles the case where a single bit is set in the mask. */
13476 Neon instructions should call it before performing bit encoding. */
13987 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13997 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14011 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14023 /* Encode insns with bit pattern:
14247 /* U bit and size field were set as part of the bitmask. */
14370 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14442 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14520 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14522 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14523 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14596 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14659 /* The U bit (rounding) comes from bit mask. */
14669 /* Size field comes from bit mask. */
14748 In this case, signed types have OP (bit 8) set to 0.
15488 /* Operand sign is unimportant, and the U bit is part of the opcode,
15515 /* For polynomial encoding the U bit must be zero, and the size must
15657 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15660 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15690 value the U bit should have for register->register moves, but
15969 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16157 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16175 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16292 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16405 /* L bit comes from bit mask. */
16877 /* Write a 32-bit thumb instruction to buf. */
17488 /* List of 16-bit instruction patterns deprecated in an IT block in
17492 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17518 as_warn (_("IT blocks containing 32-bit Thumb instructions are "
17530 as_warn (_("IT blocks containing 16-bit Thumb instructions "
17688 set those bits when Thumb-2 32-bit instructions are seen. ie.
17825 Thumb_Func bit set, then the linker will arrange for this address
17826 to have the bottom bit set, which in turn would mean that the
17828 up with the bottom bit set. Since the ARM is capable of unaligned
17836 bit of that address should be set. This will allow
20546 /* Force misaligned offsets to 32-bit variant. */
20622 /* Force misaligned targets to 32-bit variant. */
21082 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21650 negative immediate constant by altering the instruction. A bit of
21814 /* Read a 32-bit thumb instruction from buf. */
21826 /* We usually want to set the low bit on the address of thumb function
21827 symbols. In particular .word foo - . should have the low bit set.
21894 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21895 consistency with the behaviour on 32-bit hosts. Remember value
22083 _("bad immediate value for 8-bit offset (%ld)"),
22114 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22118 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22119 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22120 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22121 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22122 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22127 (bits 8..11) is present, and bit 23 is zero, even if this is
22135 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22157 /* PC-relative, 12-bit offset. */
22172 /* Writeback: 8-bit, +/- offset. */
22187 /* T-instruction: positive 8-bit offset. */
22199 /* Positive 12-bit or negative 8-bit offset. */
22282 /* No flat 12-bit imm encoding for addsw/subsw. */
22285 /* 12 bit immediate for addw/subw. */
22370 bit here because we generate PCREL_CALL for
22431 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22432 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22445 /* Set the H bit on BLX instructions. */
22589 which specifies that bit 1 of the target address will come from bit
22742 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22805 3bit ADD/SUB
22806 8bit ADD/SUB
22807 9bit ADD/SUB SP word-aligned
22808 10bit ADD PC/SP word-aligned
22889 /* 5bit shift value (0..32). LSL cannot take 32. */
22916 /* REL format relocations are limited to a 16-bit addend. */
22969 expressed as an 8-bit constant plus a rotation. */
22980 Otherwise use a SUB. Take care not to destroy the S bit. */
23019 /* If the addend is negative, clear bit 23 of the instruction.
23058 /* If the addend is negative, clear bit 23 of the instruction.
23097 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23103 /* If the addend is negative, clear bit 23 of the instruction.
23534 addresses also ought to have their bottom bit set (assuming that
24070 -mapcs-32 32-bit Program counter
24071 -mapcs-26 26-bit Program counter
24152 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
24153 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
