Lines Matching full:insn1
6215 /* Return the number of instructions that must separate INSN1 and INSN2,
6216 where INSN1 is the earlier instruction. Return the worst-case value
6220 insns_between (const struct mips_cl_insn *insn1,
6228 pinfo1 = insn1->insn_mo->pinfo;
6246 && (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1))))
6253 if (insn1->insn_opcode == INSN_ERET
6254 || insn1->insn_opcode == INSN_DERET)
6268 if ((insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULT
6269 || (insn1->insn_opcode & insn1->insn_mo->mask) == INSN_DMULTU)
6282 class1 = classify_vr4120_insn (insn1->insn_mo->name);
6301 if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
6316 /* Handle cases where INSN1 writes to a known general coprocessor
6319 mask = fpr_write_mask (insn1);
6333 /* We don't know exactly what INSN1 does. If INSN2 is
6342 control registers in cases where INSN1 does not need a general
6343 coprocessor delay. This means that INSN1 is a floating point
6355 if ((insn1->insn_mo->pinfo2 & INSN2_FORBIDDEN_SLOT)
6405 #define BASE_REG_EQ(INSN1, INSN2) \
6406 ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \
