Lines Matching refs:ISA
197 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
200 int isa;
277 Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and
282 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
293 /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1,
312 #define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
313 || mips_opts.isa == ISA_MIPS32R2 \
314 || mips_opts.isa == ISA_MIPS32R3 \
315 || mips_opts.isa == ISA_MIPS32R5 \
316 || mips_opts.isa == ISA_MIPS64 \
317 || mips_opts.isa == ISA_MIPS64R2 \
318 || mips_opts.isa == ISA_MIPS64R3 \
319 || mips_opts.isa == ISA_MIPS64R5)
356 #define ISA_IS_R6(ISA) \
357 ((ISA) == ISA_MIPS32R6 \
358 || (ISA) == ISA_MIPS64R6)
360 /* Return true if ISA supports 64 bit wide gp registers. */
361 #define ISA_HAS_64BIT_REGS(ISA) \
362 ((ISA) == ISA_MIPS3 \
363 || (ISA) == ISA_MIPS4 \
364 || (ISA) == ISA_MIPS5 \
365 || (ISA) == ISA_MIPS64 \
366 || (ISA) == ISA_MIPS64R2 \
367 || (ISA) == ISA_MIPS64R3 \
368 || (ISA) == ISA_MIPS64R5 \
369 || (ISA) == ISA_MIPS64R6)
371 /* Return true if ISA supports 64 bit wide float registers. */
372 #define ISA_HAS_64BIT_FPRS(ISA) \
373 ((ISA) == ISA_MIPS3 \
374 || (ISA) == ISA_MIPS4 \
375 || (ISA) == ISA_MIPS5 \
376 || (ISA) == ISA_MIPS32R2 \
377 || (ISA) == ISA_MIPS32R3 \
378 || (ISA) == ISA_MIPS32R5 \
379 || (ISA) == ISA_MIPS32R6 \
380 || (ISA) == ISA_MIPS64 \
381 || (ISA) == ISA_MIPS64R2 \
382 || (ISA) == ISA_MIPS64R3 \
383 || (ISA) == ISA_MIPS64R5 \
384 || (ISA) == ISA_MIPS64R6)
386 /* Return true if ISA supports 64-bit right rotate (dror et al.)
388 #define ISA_HAS_DROR(ISA) \
389 ((ISA) == ISA_MIPS64R2 \
390 || (ISA) == ISA_MIPS64R3 \
391 || (ISA) == ISA_MIPS64R5 \
392 || (ISA) == ISA_MIPS64R6 \
394 && ISA_HAS_64BIT_REGS (ISA)) \
397 /* Return true if ISA supports 32-bit right rotate (ror et al.)
399 #define ISA_HAS_ROR(ISA) \
400 ((ISA) == ISA_MIPS32R2 \
401 || (ISA) == ISA_MIPS32R3 \
402 || (ISA) == ISA_MIPS32R5 \
403 || (ISA) == ISA_MIPS32R6 \
404 || (ISA) == ISA_MIPS64R2 \
405 || (ISA) == ISA_MIPS64R3 \
406 || (ISA) == ISA_MIPS64R5 \
407 || (ISA) == ISA_MIPS64R6 \
412 /* Return true if ISA supports single-precision floats in odd registers. */
413 #define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\
414 (((ISA) == ISA_MIPS32 \
415 || (ISA) == ISA_MIPS32R2 \
416 || (ISA) == ISA_MIPS32R3 \
417 || (ISA) == ISA_MIPS32R5 \
418 || (ISA) == ISA_MIPS32R6 \
419 || (ISA) == ISA_MIPS64 \
420 || (ISA) == ISA_MIPS64R2 \
421 || (ISA) == ISA_MIPS64R3 \
422 || (ISA) == ISA_MIPS64R5 \
423 || (ISA) == ISA_MIPS64R6 \
427 /* Return true if ISA supports move to/from high part of a 64-bit
429 #define ISA_HAS_MXHC1(ISA) \
430 ((ISA) == ISA_MIPS32R2 \
431 || (ISA) == ISA_MIPS32R3 \
432 || (ISA) == ISA_MIPS32R5 \
433 || (ISA) == ISA_MIPS32R6 \
434 || (ISA) == ISA_MIPS64R2 \
435 || (ISA) == ISA_MIPS64R3 \
436 || (ISA) == ISA_MIPS64R5 \
437 || (ISA) == ISA_MIPS64R6)
439 /* Return true if ISA supports legacy NAN. */
440 #define ISA_HAS_LEGACY_NAN(ISA) \
441 ((ISA) == ISA_MIPS1 \
442 || (ISA) == ISA_MIPS2 \
443 || (ISA) == ISA_MIPS3 \
444 || (ISA) == ISA_MIPS4 \
445 || (ISA) == ISA_MIPS5 \
446 || (ISA) == ISA_MIPS32 \
447 || (ISA) == ISA_MIPS32R2 \
448 || (ISA) == ISA_MIPS32R3 \
449 || (ISA) == ISA_MIPS32R5 \
450 || (ISA) == ISA_MIPS64 \
451 || (ISA) == ISA_MIPS64R2 \
452 || (ISA) == ISA_MIPS64R3 \
453 || (ISA) == ISA_MIPS64R5)
456 (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \
461 (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \
521 ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900))
533 earlier-ISA CPUs for which CPU documentation declares that the
536 (mips_opts.isa == ISA_MIPS32 \
537 || mips_opts.isa == ISA_MIPS32R2 \
538 || mips_opts.isa == ISA_MIPS32R3 \
539 || mips_opts.isa == ISA_MIPS32R5 \
540 || mips_opts.isa == ISA_MIPS32R6 \
541 || mips_opts.isa == ISA_MIPS64 \
542 || mips_opts.isa == ISA_MIPS64R2 \
543 || mips_opts.isa == ISA_MIPS64R3 \
544 || mips_opts.isa == ISA_MIPS64R5 \
545 || mips_opts.isa == ISA_MIPS64R6 \
560 INSN_LOAD_MEMORY. These nops are only required at MIPS ISA
563 (mips_opts.isa != ISA_MIPS1 \
574 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
579 ((mips_opts.isa != ISA_MIPS1 \
580 && mips_opts.isa != ISA_MIPS2 \
581 && mips_opts.isa != ISA_MIPS3) \
590 requires at MIPS ISA level I and microMIPS mode instructions are
593 (mips_opts.isa != ISA_MIPS1 \
1359 ISA names, and
1360 ISA levels, and CPU numbers. */
1364 const char *name; /* CPU or ISA name. */
1367 int isa; /* ISA level. */
1368 int cpu; /* CPU number (default CPU if ISA). */
1371 #define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1985 /* Return the ISA revision that is currently in use, or 0 if we are
1991 if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2)
1994 if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3)
1997 if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5)
2000 if (mips_opts.isa == ISA_MIPS32R6 || mips_opts.isa == ISA_MIPS64R6)
2007 if (mips_opts.isa == ISA_MIPS32 || mips_opts.isa == ISA_MIPS64)
2026 /* Check whether the current ISA supports ASE. Issue a warning if
2037 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
2046 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
2059 size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
3242 /* Return TRUE if opcode MO is valid on the currently selected ISA, ASE
3248 int isa = mips_opts.isa;
3253 if (ISA_HAS_64BIT_REGS (mips_opts.isa))
3258 if (!opcode_is_member (mo, isa, ase, mips_opts.arch))
3285 selected ISA and architecture. */
3290 return opcode_is_member (mo, mips_opts.isa, 0, mips_opts.arch);
3861 /* Check the size of integer registers agrees with the ABI and ISA. */
3862 if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa))
3871 /* Check the size of the float registers agrees with the ABI and ISA. */
3881 if (!ISA_HAS_64BIT_FPRS (opts->isa))
3885 && !ISA_HAS_MXHC1 (opts->isa))
3892 if (ISA_IS_R6 (mips_opts.isa) && opts->single_float == 0)
3905 else if (ISA_IS_R6 (mips_opts.isa)
3910 mips_cpu_info_from_isa (mips_opts.isa)->name);
3912 if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
3914 mips_cpu_info_from_isa (opts->isa)->name);
3943 || !ISA_HAS_64BIT_REGS (file_mips_opts.isa))
3960 && ISA_HAS_64BIT_FPRS (file_mips_opts.isa))
3963 else if (ISA_IS_R6 (mips_opts.isa))
3987 if (ISA_HAS_64BIT_REGS (file_mips_opts.isa)
3992 if (file_mips_opts.isa == ISA_MIPS1 && mips_trap)
3993 as_bad (_("trap exception not supported at ISA 1"));
4004 mips_nan2008 = (ISA_HAS_LEGACY_NAN (file_mips_opts.isa)) ? 0 : 1;
4005 else if (!ISA_HAS_LEGACY_NAN (file_mips_opts.isa) && mips_nan2008 == 0)
4660 bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch)
5950 || ISA_HAS_MXHC1 (mips_opts.isa)
6929 if (ISA_IS_R6 (mips_opts.isa)
7354 /* We want MIPS16 and microMIPS debug info to use ISA-encoded addresses,
7611 gas_assert(mips_opts.mips16 || ISA_IS_R6 (mips_opts.isa));
8241 /* Record that the current instruction is invalid for the current ISA. */
8249 mips_cpu_info_from_isa (mips_opts.isa)->name);
8269 current ISA or forced_length. */
8314 all the alternatives were incompatible with the current ISA. */
8347 current ISA. There are no separate entries for extended forms so
8366 all the alternatives were incompatible with the current ISA. */
8511 #define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
8516 #define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
11465 : ISA_IS_R6 (mips_opts.isa) ? 11
11497 : ISA_IS_R6 (mips_opts.isa) ? 11
11528 : ISA_IS_R6 (mips_opts.isa) ? 9
11535 : ISA_IS_R6 (mips_opts.isa) ? 9
11607 : ISA_IS_R6 (mips_opts.isa) ? 11
11633 : ISA_IS_R6 (mips_opts.isa) ? 9
11640 : ISA_IS_R6 (mips_opts.isa) ? 9
11646 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11649 : ISA_IS_R6 (mips_opts.isa) ? 9
11660 : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
11663 : ISA_IS_R6 (mips_opts.isa) ? 9
11681 : ISA_IS_R6 (mips_opts.isa) ? 11
12266 isa))
12804 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12825 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12852 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12881 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12900 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12913 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
12932 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
12960 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
13259 gas_assert (mips_opts.isa == ISA_MIPS1);
14256 file_mips_opts.isa = ISA_MIPS1;
14260 file_mips_opts.isa = ISA_MIPS2;
14264 file_mips_opts.isa = ISA_MIPS3;
14268 file_mips_opts.isa = ISA_MIPS4;
14272 file_mips_opts.isa = ISA_MIPS5;
14276 file_mips_opts.isa = ISA_MIPS32;
14280 file_mips_opts.isa = ISA_MIPS32R2;
14284 file_mips_opts.isa = ISA_MIPS32R3;
14288 file_mips_opts.isa = ISA_MIPS32R5;
14292 file_mips_opts.isa = ISA_MIPS32R6;
14296 file_mips_opts.isa = ISA_MIPS64R2;
14300 file_mips_opts.isa = ISA_MIPS64R3;
14304 file_mips_opts.isa = ISA_MIPS64R5;
14308 file_mips_opts.isa = ISA_MIPS64R6;
14312 file_mips_opts.isa = ISA_MIPS64;
14636 /* Set up globals to tune for the ISA or processor described by INFO. */
14671 if (file_mips_opts.isa != ISA_UNKNOWN)
14673 /* Handle -mipsN. At this point, file_mips_opts.isa contains the
14674 ISA level specified by -mipsN, while arch_info->isa contains
14679 There's no harm in specifying both as long as the ISA levels
14681 if (file_mips_opts.isa != arch_info->isa)
14684 mips_cpu_info_from_isa (file_mips_opts.isa)->name,
14685 mips_cpu_info_from_isa (arch_info->isa)->name);
14688 arch_info = mips_cpu_info_from_isa (file_mips_opts.isa);
14697 if (ABI_NEEDS_64BIT_REGS (mips_abi) && !ISA_HAS_64BIT_REGS (arch_info->isa))
14702 file_mips_opts.isa = arch_info->isa;
14915 if (ISA_IS_R6 (mips_opts.isa)
15722 /* Permit the user to change the ISA and architecture on the fly.
15734 mips_opts.isa = p->isa;
15743 as_bad (_("unknown ISA level %s"), name + 4);
15747 mips_opts.isa = p->isa;
15751 as_bad (_("unknown ISA or architecture %s"), name);
15776 int prev_isa = mips_opts.isa;
15818 mips_opts.isa = file_mips_opts.isa;
15858 if (mips_opts.isa != prev_isa)
15860 switch (mips_opts.isa)
15899 as_bad (_("unknown ISA level %s"), name + 4);
16539 if (ISA_HAS_LEGACY_NAN (file_mips_opts.isa))
16543 mips_cpu_info_from_isa (file_mips_opts.isa)->name);
16984 if (mips_opts.isa == ISA_MIPS1)
17245 if ((HAVE_IN_PLACE_ADDENDS || ISA_IS_R6 (mips_opts.isa))
17589 if (mips_opts.isa == ISA_MIPS1)
18109 switch (file_mips_opts.isa)
18183 if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch)
18962 /* Return the canonical processor information for ISA (a member of the
18966 mips_cpu_info_from_isa (int isa)
18972 && isa == mips_cpu_info_table[i].isa)
19031 -mips1 generate MIPS ISA I instructions\n\
19032 -mips2 generate MIPS ISA II instructions\n\
19033 -mips3 generate MIPS ISA III instructions\n\
19034 -mips4 generate MIPS ISA IV instructions\n\
19035 -mips5 generate MIPS ISA V instructions\n\
19036 -mips32 generate MIPS32 ISA instructions\n\
19037 -mips32r2 generate MIPS32 release 2 ISA instructions\n\
19038 -mips32r3 generate MIPS32 release 3 ISA instructions\n\
19039 -mips32r5 generate MIPS32 release 5 ISA instructions\n\
19040 -mips32r6 generate MIPS32 release 6 ISA instructions\n\
19041 -mips64 generate MIPS64 ISA instructions\n\
19042 -mips64r2 generate MIPS64 release 2 ISA instructions\n\
19043 -mips64r3 generate MIPS64 release 3 ISA instructions\n\
19044 -mips64r5 generate MIPS64 release 5 ISA instructions\n\
19045 -mips64r6 generate MIPS64 release 6 ISA instructions\n\
19111 -mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
19112 -mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
