Lines Matching full:fld
77 K 16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l)
78 L 16 bit immediate, aligned 2^3. ({p}fld.d, fst.d)
79 M 16 bit immediate, aligned 2^4. ({p}fld.q, fst.q)
116 { "fld.l", 0x20000002, 0xdc000001, "1(2),g", 0 }, /* fld.l isrc1(isrc2),fdest */
117 { "fld.l", 0x24000002, 0xd8000001, "K(2),g", E_ADDR }, /* fld.l #const(isrc2),fdest */
118 { "fld.l", 0x20000003, 0xdc000000, "1(2)++,g", 0 }, /* fld.l isrc1(isrc2)++,fdest */
119 { "fld.l", 0x24000003, 0xd8000000, "K(2)++,g", E_ADDR }, /* fld.l #const(isrc2)++,fdest */
120 { "fld.d", 0x20000000, 0xdc000007, "1(2),g", 0 }, /* fld.d isrc1(isrc2),fdest */
121 { "fld.d", 0x24000000, 0xd8000007, "L(2),g", E_ADDR }, /* fld.d #const(isrc2),fdest */
122 { "fld.d", 0x20000001, 0xdc000006, "1(2)++,g", 0 }, /* fld.d isrc1(isrc2)++,fdest */
123 { "fld.d", 0x24000001, 0xd8000006, "L(2)++,g", E_ADDR }, /* fld.d #const(isrc2)++,fdest */
124 { "fld.q", 0x20000004, 0xdc000003, "1(2),g", 0 }, /* fld.q isrc1(isrc2),fdest */
125 { "fld.q", 0x24000004, 0xd8000003, "M(2),g", E_ADDR }, /* fld.q #const(isrc2),fdest */
126 { "fld.q", 0x20000005, 0xdc000002, "1(2)++,g", 0 }, /* fld.q isrc1(isrc2)++,fdest */
127 { "fld.q", 0x24000005, 0xd8000002, "M(2)++,g", E_ADDR }, /* fld.q #const(isrc2)++,fdest */
