Lines Matching refs:F_UNBR
716 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+rs2 */
717 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1,%g0 */
718 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+X */
719 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */
720 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X+rs1 */
721 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett X */
722 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* rett rs1+0 */
729 { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %i7+8,%g0 */
730 { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %o7+8,%g0 */
1177 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1182 cond ("b", "ta", CONDA, F_UNBR),
1184 cond ("ba", "t", CONDA, F_UNBR|F_ALIAS),
1509 CONDFC ("fb", "cb", 0x8, F_UNBR),
1510 CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS),
1518 CONDFCL ("fbn", "cbn", 0x0, F_UNBR),
1536 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+rs2,%g0 */
1537 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,%g0 */
1538 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+i,%g0 */
1539 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl i+rs1,%g0 */
1540 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,%g0 */
1541 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,%g0 */
