Lines Matching defs:VR2
1281 #define VR2 (VR1 + 1)1284 #define CACHEOP (VR2 + 1)1617 { "ldtc.vr", two (0x07e0, 0x0832), two (0x07e0, 0xffff), {R1, VR2}, 0, PROCESSOR_V850E3V5_UP },
