1 //===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the ARM specific subclass of TargetMachine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H 15 #define LLVM_LIB_TARGET_ARM_ARMTARGETMACHINE_H 16 17 #include "ARMInstrInfo.h" 18 #include "ARMSubtarget.h" 19 #include "llvm/IR/DataLayout.h" 20 #include "llvm/Target/TargetMachine.h" 21 22 namespace llvm { 23 24 class ARMBaseTargetMachine : public LLVMTargetMachine { 25 public: 26 enum ARMABI { 27 ARM_ABI_UNKNOWN, 28 ARM_ABI_APCS, 29 ARM_ABI_AAPCS, // ARM EABI 30 ARM_ABI_AAPCS16 31 } TargetABI; 32 33 protected: 34 std::unique_ptr<TargetLoweringObjectFile> TLOF; 35 ARMSubtarget Subtarget; 36 bool isLittle; 37 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap; 38 39 public: 40 ARMBaseTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 41 StringRef FS, const TargetOptions &Options, 42 Reloc::Model RM, CodeModel::Model CM, 43 CodeGenOpt::Level OL, bool isLittle); 44 ~ARMBaseTargetMachine() override; 45 46 const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } 47 const ARMSubtarget *getSubtargetImpl(const Function &F) const override; 48 bool isLittleEndian() const { return isLittle; } 49 50 /// \brief Get the TargetIRAnalysis for this target. 51 TargetIRAnalysis getTargetIRAnalysis() override; 52 53 // Pass Pipeline Configuration 54 TargetPassConfig *createPassConfig(PassManagerBase &PM) override; 55 56 TargetLoweringObjectFile *getObjFileLowering() const override { 57 return TLOF.get(); 58 } 59 }; 60 61 /// ARMTargetMachine - ARM target machine. 62 /// 63 class ARMTargetMachine : public ARMBaseTargetMachine { 64 virtual void anchor(); 65 public: 66 ARMTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 67 StringRef FS, const TargetOptions &Options, Reloc::Model RM, 68 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); 69 }; 70 71 /// ARMLETargetMachine - ARM little endian target machine. 72 /// 73 class ARMLETargetMachine : public ARMTargetMachine { 74 void anchor() override; 75 public: 76 ARMLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, 77 StringRef FS, const TargetOptions &Options, 78 Reloc::Model RM, CodeModel::Model CM, 79 CodeGenOpt::Level OL); 80 }; 81 82 /// ARMBETargetMachine - ARM big endian target machine. 83 /// 84 class ARMBETargetMachine : public ARMTargetMachine { 85 void anchor() override; 86 public: 87 ARMBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, 88 StringRef FS, const TargetOptions &Options, 89 Reloc::Model RM, CodeModel::Model CM, 90 CodeGenOpt::Level OL); 91 }; 92 93 /// ThumbTargetMachine - Thumb target machine. 94 /// Due to the way architectures are handled, this represents both 95 /// Thumb-1 and Thumb-2. 96 /// 97 class ThumbTargetMachine : public ARMBaseTargetMachine { 98 virtual void anchor(); 99 public: 100 ThumbTargetMachine(const Target &T, const Triple &TT, StringRef CPU, 101 StringRef FS, const TargetOptions &Options, 102 Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, 103 bool isLittle); 104 }; 105 106 /// ThumbLETargetMachine - Thumb little endian target machine. 107 /// 108 class ThumbLETargetMachine : public ThumbTargetMachine { 109 void anchor() override; 110 public: 111 ThumbLETargetMachine(const Target &T, const Triple &TT, StringRef CPU, 112 StringRef FS, const TargetOptions &Options, 113 Reloc::Model RM, CodeModel::Model CM, 114 CodeGenOpt::Level OL); 115 }; 116 117 /// ThumbBETargetMachine - Thumb big endian target machine. 118 /// 119 class ThumbBETargetMachine : public ThumbTargetMachine { 120 void anchor() override; 121 public: 122 ThumbBETargetMachine(const Target &T, const Triple &TT, StringRef CPU, 123 StringRef FS, const TargetOptions &Options, 124 Reloc::Model RM, CodeModel::Model CM, 125 CodeGenOpt::Level OL); 126 }; 127 128 } // end namespace llvm 129 130 #endif 131
