1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith (at) tungstengraphics.com> 30 */ 31 32 33 #ifndef BRWCONTEXT_INC 34 #define BRWCONTEXT_INC 35 36 #include "intel_context.h" 37 #include "brw_structs.h" 38 #include "main/imports.h" 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* Glossary: 45 * 46 * URB - uniform resource buffer. A mid-sized buffer which is 47 * partitioned between the fixed function units and used for passing 48 * values (vertices, primitives, constants) between them. 49 * 50 * CURBE - constant URB entry. An urb region (entry) used to hold 51 * constant values which the fixed function units can be instructed to 52 * preload into the GRF when spawning a thread. 53 * 54 * VUE - vertex URB entry. An urb entry holding a vertex and usually 55 * a vertex header. The header contains control information and 56 * things like primitive type, Begin/end flags and clip codes. 57 * 58 * PUE - primitive URB entry. An urb entry produced by the setup (SF) 59 * unit holding rasterization and interpolation parameters. 60 * 61 * GRF - general register file. One of several register files 62 * addressable by programmed threads. The inputs (r0, payload, curbe, 63 * urb) of the thread are preloaded to this area before the thread is 64 * spawned. The registers are individually 8 dwords wide and suitable 65 * for general usage. Registers holding thread input values are not 66 * special and may be overwritten. 67 * 68 * MRF - message register file. Threads communicate (and terminate) 69 * by sending messages. Message parameters are placed in contiguous 70 * MRF registers. All program output is via these messages. URB 71 * entries are populated by sending a message to the shared URB 72 * function containing the new data, together with a control word, 73 * often an unmodified copy of R0. 74 * 75 * R0 - GRF register 0. Typically holds control information used when 76 * sending messages to other threads. 77 * 78 * EU or GEN4 EU: The name of the programmable subsystem of the 79 * i965 hardware. Threads are executed by the EU, the registers 80 * described above are part of the EU architecture. 81 * 82 * Fixed function units: 83 * 84 * CS - Command streamer. Notional first unit, little software 85 * interaction. Holds the URB entries used for constant data, ie the 86 * CURBEs. 87 * 88 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of 89 * this unit is responsible for pulling vertices out of vertex buffers 90 * in vram and injecting them into the processing pipe as VUEs. If 91 * enabled, it first passes them to a VS thread which is a good place 92 * for the driver to implement any active vertex shader. 93 * 94 * GS - Geometry Shader. This corresponds to a new DX10 concept. If 95 * enabled, incoming strips etc are passed to GS threads in individual 96 * line/triangle/point units. The GS thread may perform arbitary 97 * computation and emit whatever primtives with whatever vertices it 98 * chooses. This makes GS an excellent place to implement GL's 99 * unfilled polygon modes, though of course it is capable of much 100 * more. Additionally, GS is used to translate away primitives not 101 * handled by latter units, including Quads and Lineloops. 102 * 103 * CS - Clipper. Mesa's clipping algorithms are imported to run on 104 * this unit. The fixed function part performs cliptesting against 105 * the 6 fixed clipplanes and makes descisions on whether or not the 106 * incoming primitive needs to be passed to a thread for clipping. 107 * User clip planes are handled via cooperation with the VS thread. 108 * 109 * SF - Strips Fans or Setup: Triangles are prepared for 110 * rasterization. Interpolation coefficients are calculated. 111 * Flatshading and two-side lighting usually performed here. 112 * 113 * WM - Windower. Interpolation of vertex attributes performed here. 114 * Fragment shader implemented here. SIMD aspects of EU taken full 115 * advantage of, as pixels are processed in blocks of 16. 116 * 117 * CC - Color Calculator. No EU threads associated with this unit. 118 * Handles blending and (presumably) depth and stencil testing. 119 */ 120 121 122 #define BRW_MAX_CURBE (32*16) 123 124 struct brw_context; 125 struct brw_instruction; 126 struct brw_vs_prog_key; 127 struct brw_wm_prog_key; 128 struct brw_wm_prog_data; 129 130 enum brw_state_id { 131 BRW_STATE_URB_FENCE, 132 BRW_STATE_FRAGMENT_PROGRAM, 133 BRW_STATE_VERTEX_PROGRAM, 134 BRW_STATE_INPUT_DIMENSIONS, 135 BRW_STATE_CURBE_OFFSETS, 136 BRW_STATE_REDUCED_PRIMITIVE, 137 BRW_STATE_PRIMITIVE, 138 BRW_STATE_CONTEXT, 139 BRW_STATE_WM_INPUT_DIMENSIONS, 140 BRW_STATE_PSP, 141 BRW_STATE_SURFACES, 142 BRW_STATE_VS_BINDING_TABLE, 143 BRW_STATE_GS_BINDING_TABLE, 144 BRW_STATE_PS_BINDING_TABLE, 145 BRW_STATE_INDICES, 146 BRW_STATE_VERTICES, 147 BRW_STATE_BATCH, 148 BRW_STATE_NR_WM_SURFACES, 149 BRW_STATE_NR_VS_SURFACES, 150 BRW_STATE_INDEX_BUFFER, 151 BRW_STATE_VS_CONSTBUF, 152 BRW_STATE_PROGRAM_CACHE, 153 BRW_STATE_STATE_BASE_ADDRESS, 154 BRW_STATE_SOL_INDICES, 155 }; 156 157 #define BRW_NEW_URB_FENCE (1 << BRW_STATE_URB_FENCE) 158 #define BRW_NEW_FRAGMENT_PROGRAM (1 << BRW_STATE_FRAGMENT_PROGRAM) 159 #define BRW_NEW_VERTEX_PROGRAM (1 << BRW_STATE_VERTEX_PROGRAM) 160 #define BRW_NEW_INPUT_DIMENSIONS (1 << BRW_STATE_INPUT_DIMENSIONS) 161 #define BRW_NEW_CURBE_OFFSETS (1 << BRW_STATE_CURBE_OFFSETS) 162 #define BRW_NEW_REDUCED_PRIMITIVE (1 << BRW_STATE_REDUCED_PRIMITIVE) 163 #define BRW_NEW_PRIMITIVE (1 << BRW_STATE_PRIMITIVE) 164 #define BRW_NEW_CONTEXT (1 << BRW_STATE_CONTEXT) 165 #define BRW_NEW_WM_INPUT_DIMENSIONS (1 << BRW_STATE_WM_INPUT_DIMENSIONS) 166 #define BRW_NEW_PSP (1 << BRW_STATE_PSP) 167 #define BRW_NEW_SURFACES (1 << BRW_STATE_SURFACES) 168 #define BRW_NEW_VS_BINDING_TABLE (1 << BRW_STATE_VS_BINDING_TABLE) 169 #define BRW_NEW_GS_BINDING_TABLE (1 << BRW_STATE_GS_BINDING_TABLE) 170 #define BRW_NEW_PS_BINDING_TABLE (1 << BRW_STATE_PS_BINDING_TABLE) 171 #define BRW_NEW_INDICES (1 << BRW_STATE_INDICES) 172 #define BRW_NEW_VERTICES (1 << BRW_STATE_VERTICES) 173 /** 174 * Used for any batch entry with a relocated pointer that will be used 175 * by any 3D rendering. 176 */ 177 #define BRW_NEW_BATCH (1 << BRW_STATE_BATCH) 178 /** \see brw.state.depth_region */ 179 #define BRW_NEW_INDEX_BUFFER (1 << BRW_STATE_INDEX_BUFFER) 180 #define BRW_NEW_VS_CONSTBUF (1 << BRW_STATE_VS_CONSTBUF) 181 #define BRW_NEW_PROGRAM_CACHE (1 << BRW_STATE_PROGRAM_CACHE) 182 #define BRW_NEW_STATE_BASE_ADDRESS (1 << BRW_STATE_STATE_BASE_ADDRESS) 183 #define BRW_NEW_SOL_INDICES (1 << BRW_STATE_SOL_INDICES) 184 185 struct brw_state_flags { 186 /** State update flags signalled by mesa internals */ 187 GLuint mesa; 188 /** 189 * State update flags signalled as the result of brw_tracked_state updates 190 */ 191 GLuint brw; 192 /** State update flags signalled by brw_state_cache.c searches */ 193 GLuint cache; 194 }; 195 196 #define AUB_TRACE_TYPE_MASK 0x0000ff00 197 #define AUB_TRACE_TYPE_NOTYPE (0 << 8) 198 #define AUB_TRACE_TYPE_BATCH (1 << 8) 199 #define AUB_TRACE_TYPE_VERTEX_BUFFER (5 << 8) 200 #define AUB_TRACE_TYPE_2D_MAP (6 << 8) 201 #define AUB_TRACE_TYPE_CUBE_MAP (7 << 8) 202 #define AUB_TRACE_TYPE_VOLUME_MAP (9 << 8) 203 #define AUB_TRACE_TYPE_1D_MAP (10 << 8) 204 #define AUB_TRACE_TYPE_CONSTANT_BUFFER (11 << 8) 205 #define AUB_TRACE_TYPE_CONSTANT_URB (12 << 8) 206 #define AUB_TRACE_TYPE_INDEX_BUFFER (13 << 8) 207 #define AUB_TRACE_TYPE_GENERAL (14 << 8) 208 #define AUB_TRACE_TYPE_SURFACE (15 << 8) 209 210 /** 211 * state_struct_type enum values are encoded with the top 16 bits representing 212 * the type to be delivered to the .aub file, and the bottom 16 bits 213 * representing the subtype. This macro performs the encoding. 214 */ 215 #define ENCODE_SS_TYPE(type, subtype) (((type) << 16) | (subtype)) 216 217 enum state_struct_type { 218 AUB_TRACE_VS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 1), 219 AUB_TRACE_GS_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 2), 220 AUB_TRACE_CLIP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 3), 221 AUB_TRACE_SF_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 4), 222 AUB_TRACE_WM_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 5), 223 AUB_TRACE_CC_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 6), 224 AUB_TRACE_CLIP_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 7), 225 AUB_TRACE_SF_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 8), 226 AUB_TRACE_CC_VP_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x9), 227 AUB_TRACE_SAMPLER_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xa), 228 AUB_TRACE_KERNEL_INSTRUCTIONS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xb), 229 AUB_TRACE_SCRATCH_SPACE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xc), 230 AUB_TRACE_SAMPLER_DEFAULT_COLOR = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0xd), 231 232 AUB_TRACE_SCISSOR_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x15), 233 AUB_TRACE_BLEND_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x16), 234 AUB_TRACE_DEPTH_STENCIL_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_GENERAL, 0x17), 235 236 AUB_TRACE_VERTEX_BUFFER = ENCODE_SS_TYPE(AUB_TRACE_TYPE_VERTEX_BUFFER, 0), 237 AUB_TRACE_BINDING_TABLE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x100), 238 AUB_TRACE_SURFACE_STATE = ENCODE_SS_TYPE(AUB_TRACE_TYPE_SURFACE, 0x200), 239 AUB_TRACE_VS_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 0), 240 AUB_TRACE_WM_CONSTANTS = ENCODE_SS_TYPE(AUB_TRACE_TYPE_CONSTANT_BUFFER, 1), 241 }; 242 243 /** 244 * Decode a state_struct_type value to determine the type that should be 245 * stored in the .aub file. 246 */ 247 static inline uint32_t AUB_TRACE_TYPE(enum state_struct_type ss_type) 248 { 249 return (ss_type & 0xFFFF0000) >> 16; 250 } 251 252 /** 253 * Decode a state_struct_type value to determine the subtype that should be 254 * stored in the .aub file. 255 */ 256 static inline uint32_t AUB_TRACE_SUBTYPE(enum state_struct_type ss_type) 257 { 258 return ss_type & 0xFFFF; 259 } 260 261 /** Subclass of Mesa vertex program */ 262 struct brw_vertex_program { 263 struct gl_vertex_program program; 264 GLuint id; 265 bool use_const_buffer; 266 }; 267 268 269 /** Subclass of Mesa fragment program */ 270 struct brw_fragment_program { 271 struct gl_fragment_program program; 272 GLuint id; /**< serial no. to identify frag progs, never re-used */ 273 }; 274 275 struct brw_shader { 276 struct gl_shader base; 277 278 bool compiled_once; 279 280 /** Shader IR transformed for native compile, at link time. */ 281 struct exec_list *ir; 282 }; 283 284 struct brw_shader_program { 285 struct gl_shader_program base; 286 }; 287 288 /* Data about a particular attempt to compile a program. Note that 289 * there can be many of these, each in a different GL state 290 * corresponding to a different brw_wm_prog_key struct, with different 291 * compiled programs: 292 */ 293 struct brw_wm_prog_data { 294 GLuint curb_read_length; 295 GLuint urb_read_length; 296 297 GLuint first_curbe_grf; 298 GLuint first_curbe_grf_16; 299 GLuint reg_blocks; 300 GLuint reg_blocks_16; 301 GLuint total_scratch; 302 303 GLuint nr_params; /**< number of float params/constants */ 304 GLuint nr_pull_params; 305 bool error; 306 bool dual_src_blend; 307 int dispatch_width; 308 uint32_t prog_offset_16; 309 310 /** 311 * Mask of which interpolation modes are required by the fragment shader. 312 * Used in hardware setup on gen6+. 313 */ 314 uint32_t barycentric_interp_modes; 315 316 /* Pointer to tracked values (only valid once 317 * _mesa_load_state_parameters has been called at runtime). 318 */ 319 const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */ 320 const float *pull_param[MAX_UNIFORMS * 4]; 321 }; 322 323 /** 324 * Enum representing the i965-specific vertex results that don't correspond 325 * exactly to any element of gl_vert_result. The values of this enum are 326 * assigned such that they don't conflict with gl_vert_result. 327 */ 328 typedef enum 329 { 330 BRW_VERT_RESULT_NDC = VERT_RESULT_MAX, 331 BRW_VERT_RESULT_HPOS_DUPLICATE, 332 BRW_VERT_RESULT_PAD, 333 /* 334 * It's actually not a vert_result but just a _mark_ to let sf aware that 335 * he need do something special to handle gl_PointCoord builtin variable 336 * correctly. see compile_sf_prog() for more info. 337 */ 338 BRW_VERT_RESULT_PNTC, 339 BRW_VERT_RESULT_MAX 340 } brw_vert_result; 341 342 343 /** 344 * Data structure recording the relationship between the gl_vert_result enum 345 * and "slots" within the vertex URB entry (VUE). A "slot" is defined as a 346 * single octaword within the VUE (128 bits). 347 * 348 * Note that each BRW register contains 256 bits (2 octawords), so when 349 * accessing the VUE in URB_NOSWIZZLE mode, each register corresponds to two 350 * consecutive VUE slots. When accessing the VUE in URB_INTERLEAVED mode (as 351 * in a vertex shader), each register corresponds to a single VUE slot, since 352 * it contains data for two separate vertices. 353 */ 354 struct brw_vue_map { 355 /** 356 * Map from gl_vert_result value to VUE slot. For gl_vert_results that are 357 * not stored in a slot (because they are not written, or because 358 * additional processing is applied before storing them in the VUE), the 359 * value is -1. 360 */ 361 int vert_result_to_slot[BRW_VERT_RESULT_MAX]; 362 363 /** 364 * Map from VUE slot to gl_vert_result value. For slots that do not 365 * directly correspond to a gl_vert_result, the value comes from 366 * brw_vert_result. 367 * 368 * For slots that are not in use, the value is BRW_VERT_RESULT_MAX (this 369 * simplifies code that uses the value stored in slot_to_vert_result to 370 * create a bit mask). 371 */ 372 int slot_to_vert_result[BRW_VERT_RESULT_MAX]; 373 374 /** 375 * Total number of VUE slots in use 376 */ 377 int num_slots; 378 }; 379 380 /** 381 * Convert a VUE slot number into a byte offset within the VUE. 382 */ 383 static inline GLuint brw_vue_slot_to_offset(GLuint slot) 384 { 385 return 16*slot; 386 } 387 388 /** 389 * Convert a vert_result into a byte offset within the VUE. 390 */ 391 static inline GLuint brw_vert_result_to_offset(struct brw_vue_map *vue_map, 392 GLuint vert_result) 393 { 394 return brw_vue_slot_to_offset(vue_map->vert_result_to_slot[vert_result]); 395 } 396 397 398 struct brw_sf_prog_data { 399 GLuint urb_read_length; 400 GLuint total_grf; 401 402 /* Each vertex may have upto 12 attributes, 4 components each, 403 * except WPOS which requires only 2. (11*4 + 2) == 44 ==> 11 404 * rows. 405 * 406 * Actually we use 4 for each, so call it 12 rows. 407 */ 408 GLuint urb_entry_size; 409 }; 410 411 struct brw_clip_prog_data { 412 GLuint curb_read_length; /* user planes? */ 413 GLuint clip_mode; 414 GLuint urb_read_length; 415 GLuint total_grf; 416 }; 417 418 struct brw_gs_prog_data { 419 GLuint urb_read_length; 420 GLuint total_grf; 421 422 /** 423 * Gen6 transform feedback: Amount by which the streaming vertex buffer 424 * indices should be incremented each time the GS is invoked. 425 */ 426 unsigned svbi_postincrement_value; 427 }; 428 429 struct brw_vs_prog_data { 430 struct brw_vue_map vue_map; 431 432 GLuint curb_read_length; 433 GLuint urb_read_length; 434 GLuint total_grf; 435 GLbitfield64 outputs_written; 436 GLuint nr_params; /**< number of float params/constants */ 437 GLuint nr_pull_params; /**< number of dwords referenced by pull_param[] */ 438 GLuint total_scratch; 439 440 GLbitfield64 inputs_read; 441 442 /* Used for calculating urb partitions: 443 */ 444 GLuint urb_entry_size; 445 446 const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */ 447 const float *pull_param[MAX_UNIFORMS * 4]; 448 449 bool uses_new_param_layout; 450 bool uses_vertexid; 451 bool userclip; 452 453 int num_surfaces; 454 }; 455 456 457 /* Size == 0 if output either not written, or always [0,0,0,1] 458 */ 459 struct brw_vs_ouput_sizes { 460 GLubyte output_size[VERT_RESULT_MAX]; 461 }; 462 463 464 /** Number of texture sampler units */ 465 #define BRW_MAX_TEX_UNIT 16 466 467 /** Max number of render targets in a shader */ 468 #define BRW_MAX_DRAW_BUFFERS 8 469 470 /** 471 * Max number of binding table entries used for stream output. 472 * 473 * From the OpenGL 3.0 spec, table 6.44 (Transform Feedback State), the 474 * minimum value of MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS is 64. 475 * 476 * On Gen6, the size of transform feedback data is limited not by the number 477 * of components but by the number of binding table entries we set aside. We 478 * use one binding table entry for a float, one entry for a vector, and one 479 * entry per matrix column. Since the only way we can communicate our 480 * transform feedback capabilities to the client is via 481 * MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS, we need to plan for the 482 * worst case, in which all the varyings are floats, so we use up one binding 483 * table entry per component. Therefore we need to set aside at least 64 484 * binding table entries for use by transform feedback. 485 * 486 * Note: since we don't currently pack varyings, it is currently impossible 487 * for the client to actually use up all of these binding table entries--if 488 * all of their varyings were floats, they would run out of varying slots and 489 * fail to link. But that's a bug, so it seems prudent to go ahead and 490 * allocate the number of binding table entries we will need once the bug is 491 * fixed. 492 */ 493 #define BRW_MAX_SOL_BINDINGS 64 494 495 /** Maximum number of actual buffers used for stream output */ 496 #define BRW_MAX_SOL_BUFFERS 4 497 498 #define BRW_MAX_WM_UBOS 12 499 #define BRW_MAX_VS_UBOS 12 500 501 /** 502 * Helpers to create Surface Binding Table indexes for draw buffers, 503 * textures, and constant buffers. 504 * 505 * Shader threads access surfaces via numeric handles, rather than directly 506 * using pointers. The binding table maps these numeric handles to the 507 * address of the actual buffer. 508 * 509 * For example, a shader might ask to sample from "surface 7." In this case, 510 * bind[7] would contain a pointer to a texture. 511 * 512 * Currently, our WM binding tables are (arbitrarily) programmed as follows: 513 * 514 * +-------------------------------+ 515 * | 0 | Draw buffer 0 | 516 * | . | . | 517 * | : | : | 518 * | 7 | Draw buffer 7 | 519 * |-----|-------------------------| 520 * | 8 | WM Pull Constant Buffer | 521 * |-----|-------------------------| 522 * | 9 | Texture 0 | 523 * | . | . | 524 * | : | : | 525 * | 24 | Texture 15 | 526 * |-----|-------------------------| 527 * | 25 | UBO 0 | 528 * | . | . | 529 * | : | : | 530 * | 36 | UBO 11 | 531 * +-------------------------------+ 532 * 533 * Our VS binding tables are programmed as follows: 534 * 535 * +-----+-------------------------+ 536 * | 0 | VS Pull Constant Buffer | 537 * +-----+-------------------------+ 538 * | 1 | Texture 0 | 539 * | . | . | 540 * | : | : | 541 * | 16 | Texture 15 | 542 * +-----+-------------------------+ 543 * | 17 | UBO 0 | 544 * | . | . | 545 * | : | : | 546 * | 28 | UBO 11 | 547 * +-------------------------------+ 548 * 549 * Our (gen6) GS binding tables are programmed as follows: 550 * 551 * +-----+-------------------------+ 552 * | 0 | SOL Binding 0 | 553 * | . | . | 554 * | : | : | 555 * | 63 | SOL Binding 63 | 556 * +-----+-------------------------+ 557 * 558 * Note that nothing actually uses the SURF_INDEX_DRAW macro, so it has to be 559 * the identity function or things will break. We do want to keep draw buffers 560 * first so we can use headerless render target writes for RT 0. 561 */ 562 #define SURF_INDEX_DRAW(d) (d) 563 #define SURF_INDEX_FRAG_CONST_BUFFER (BRW_MAX_DRAW_BUFFERS + 1) 564 #define SURF_INDEX_TEXTURE(t) (BRW_MAX_DRAW_BUFFERS + 2 + (t)) 565 #define SURF_INDEX_WM_UBO(u) (SURF_INDEX_TEXTURE(BRW_MAX_TEX_UNIT) + u) 566 567 /** Maximum size of the binding table. */ 568 #define BRW_MAX_WM_SURFACES SURF_INDEX_WM_UBO(BRW_MAX_WM_UBOS) 569 570 #define SURF_INDEX_VERT_CONST_BUFFER (0) 571 #define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t)) 572 #define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) + u) 573 #define BRW_MAX_VS_SURFACES SURF_INDEX_VS_UBO(BRW_MAX_VS_UBOS) 574 575 #define SURF_INDEX_SOL_BINDING(t) ((t)) 576 #define BRW_MAX_GS_SURFACES SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS) 577 578 enum brw_cache_id { 579 BRW_BLEND_STATE, 580 BRW_DEPTH_STENCIL_STATE, 581 BRW_COLOR_CALC_STATE, 582 BRW_CC_VP, 583 BRW_CC_UNIT, 584 BRW_WM_PROG, 585 BRW_BLORP_BLIT_PROG, 586 BRW_SAMPLER, 587 BRW_WM_UNIT, 588 BRW_SF_PROG, 589 BRW_SF_VP, 590 BRW_SF_UNIT, /* scissor state on gen6 */ 591 BRW_VS_UNIT, 592 BRW_VS_PROG, 593 BRW_GS_UNIT, 594 BRW_GS_PROG, 595 BRW_CLIP_VP, 596 BRW_CLIP_UNIT, 597 BRW_CLIP_PROG, 598 599 BRW_MAX_CACHE 600 }; 601 602 struct brw_cache_item { 603 /** 604 * Effectively part of the key, cache_id identifies what kind of state 605 * buffer is involved, and also which brw->state.dirty.cache flag should 606 * be set when this cache item is chosen. 607 */ 608 enum brw_cache_id cache_id; 609 /** 32-bit hash of the key data */ 610 GLuint hash; 611 GLuint key_size; /* for variable-sized keys */ 612 GLuint aux_size; 613 const void *key; 614 615 uint32_t offset; 616 uint32_t size; 617 618 struct brw_cache_item *next; 619 }; 620 621 622 623 struct brw_cache { 624 struct brw_context *brw; 625 626 struct brw_cache_item **items; 627 drm_intel_bo *bo; 628 GLuint size, n_items; 629 630 uint32_t next_offset; 631 bool bo_used_by_gpu; 632 }; 633 634 635 /* Considered adding a member to this struct to document which flags 636 * an update might raise so that ordering of the state atoms can be 637 * checked or derived at runtime. Dropped the idea in favor of having 638 * a debug mode where the state is monitored for flags which are 639 * raised that have already been tested against. 640 */ 641 struct brw_tracked_state { 642 struct brw_state_flags dirty; 643 void (*emit)( struct brw_context *brw ); 644 }; 645 646 /* Flags for brw->state.cache. 647 */ 648 #define CACHE_NEW_BLEND_STATE (1<<BRW_BLEND_STATE) 649 #define CACHE_NEW_DEPTH_STENCIL_STATE (1<<BRW_DEPTH_STENCIL_STATE) 650 #define CACHE_NEW_COLOR_CALC_STATE (1<<BRW_COLOR_CALC_STATE) 651 #define CACHE_NEW_CC_VP (1<<BRW_CC_VP) 652 #define CACHE_NEW_CC_UNIT (1<<BRW_CC_UNIT) 653 #define CACHE_NEW_WM_PROG (1<<BRW_WM_PROG) 654 #define CACHE_NEW_SAMPLER (1<<BRW_SAMPLER) 655 #define CACHE_NEW_WM_UNIT (1<<BRW_WM_UNIT) 656 #define CACHE_NEW_SF_PROG (1<<BRW_SF_PROG) 657 #define CACHE_NEW_SF_VP (1<<BRW_SF_VP) 658 #define CACHE_NEW_SF_UNIT (1<<BRW_SF_UNIT) 659 #define CACHE_NEW_VS_UNIT (1<<BRW_VS_UNIT) 660 #define CACHE_NEW_VS_PROG (1<<BRW_VS_PROG) 661 #define CACHE_NEW_GS_UNIT (1<<BRW_GS_UNIT) 662 #define CACHE_NEW_GS_PROG (1<<BRW_GS_PROG) 663 #define CACHE_NEW_CLIP_VP (1<<BRW_CLIP_VP) 664 #define CACHE_NEW_CLIP_UNIT (1<<BRW_CLIP_UNIT) 665 #define CACHE_NEW_CLIP_PROG (1<<BRW_CLIP_PROG) 666 667 struct brw_cached_batch_item { 668 struct header *header; 669 GLuint sz; 670 struct brw_cached_batch_item *next; 671 }; 672 673 674 675 /* Protect against a future where VERT_ATTRIB_MAX > 32. Wouldn't life 676 * be easier if C allowed arrays of packed elements? 677 */ 678 #define ATTRIB_BIT_DWORDS ((VERT_ATTRIB_MAX+31)/32) 679 680 struct brw_vertex_buffer { 681 /** Buffer object containing the uploaded vertex data */ 682 drm_intel_bo *bo; 683 uint32_t offset; 684 /** Byte stride between elements in the uploaded array */ 685 GLuint stride; 686 GLuint step_rate; 687 }; 688 struct brw_vertex_element { 689 const struct gl_client_array *glarray; 690 691 int buffer; 692 693 /** The corresponding Mesa vertex attribute */ 694 gl_vert_attrib attrib; 695 /** Size of a complete element */ 696 GLuint element_size; 697 /** Offset of the first element within the buffer object */ 698 unsigned int offset; 699 }; 700 701 702 703 struct brw_vertex_info { 704 GLuint sizes[ATTRIB_BIT_DWORDS * 2]; /* sizes:2[VERT_ATTRIB_MAX] */ 705 }; 706 707 struct brw_query_object { 708 struct gl_query_object Base; 709 710 /** Last query BO associated with this query. */ 711 drm_intel_bo *bo; 712 /** First index in bo with query data for this object. */ 713 int first_index; 714 /** Last index in bo with query data for this object. */ 715 int last_index; 716 }; 717 718 719 /** 720 * brw_context is derived from intel_context. 721 */ 722 struct brw_context 723 { 724 struct intel_context intel; /**< base class, must be first field */ 725 GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */ 726 727 bool emit_state_always; 728 bool has_surface_tile_offset; 729 bool has_compr4; 730 bool has_negative_rhw_bug; 731 bool has_aa_line_parameters; 732 bool has_pln; 733 bool precompile; 734 735 /** 736 * Some versions of Gen hardware don't do centroid interpolation correctly 737 * on unlit pixels, causing incorrect values for derivatives near triangle 738 * edges. Enabling this flag causes the fragment shader to use 739 * non-centroid interpolation for unlit pixels, at the expense of two extra 740 * fragment shader instructions. 741 */ 742 bool needs_unlit_centroid_workaround; 743 744 struct { 745 struct brw_state_flags dirty; 746 } state; 747 748 struct brw_cache cache; 749 struct brw_cached_batch_item *cached_batch_items; 750 751 struct { 752 struct brw_vertex_element inputs[VERT_ATTRIB_MAX]; 753 struct brw_vertex_buffer buffers[VERT_ATTRIB_MAX]; 754 struct { 755 uint32_t handle; 756 uint32_t offset; 757 uint32_t stride; 758 uint32_t step_rate; 759 } current_buffers[VERT_ATTRIB_MAX]; 760 761 struct brw_vertex_element *enabled[VERT_ATTRIB_MAX]; 762 GLuint nr_enabled; 763 GLuint nr_buffers, nr_current_buffers; 764 765 /* Summary of size and varying of active arrays, so we can check 766 * for changes to this state: 767 */ 768 struct brw_vertex_info info; 769 unsigned int min_index, max_index; 770 771 /* Offset from start of vertex buffer so we can avoid redefining 772 * the same VB packed over and over again. 773 */ 774 unsigned int start_vertex_bias; 775 } vb; 776 777 struct { 778 /** 779 * Index buffer for this draw_prims call. 780 * 781 * Updates are signaled by BRW_NEW_INDICES. 782 */ 783 const struct _mesa_index_buffer *ib; 784 785 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */ 786 drm_intel_bo *bo; 787 GLuint type; 788 789 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can 790 * avoid re-uploading the IB packet over and over if we're actually 791 * referencing the same index buffer. 792 */ 793 unsigned int start_vertex_offset; 794 } ib; 795 796 /* Active vertex program: 797 */ 798 const struct gl_vertex_program *vertex_program; 799 const struct gl_fragment_program *fragment_program; 800 801 /* hw-dependent 3DSTATE_VF_STATISTICS opcode */ 802 uint32_t CMD_VF_STATISTICS; 803 /* hw-dependent 3DSTATE_PIPELINE_SELECT opcode */ 804 uint32_t CMD_PIPELINE_SELECT; 805 806 /** 807 * Platform specific constants containing the maximum number of threads 808 * for each pipeline stage. 809 */ 810 int max_vs_threads; 811 int max_gs_threads; 812 int max_wm_threads; 813 814 /* BRW_NEW_URB_ALLOCATIONS: 815 */ 816 struct { 817 GLuint vsize; /* vertex size plus header in urb registers */ 818 GLuint csize; /* constant buffer size in urb registers */ 819 GLuint sfsize; /* setup data size in urb registers */ 820 821 bool constrained; 822 823 GLuint max_vs_entries; /* Maximum number of VS entries */ 824 GLuint max_gs_entries; /* Maximum number of GS entries */ 825 826 GLuint nr_vs_entries; 827 GLuint nr_gs_entries; 828 GLuint nr_clip_entries; 829 GLuint nr_sf_entries; 830 GLuint nr_cs_entries; 831 832 /* gen6: 833 * The length of each URB entry owned by the VS (or GS), as 834 * a number of 1024-bit (128-byte) rows. Should be >= 1. 835 * 836 * gen7: Same meaning, but in 512-bit (64-byte) rows. 837 */ 838 GLuint vs_size; 839 GLuint gs_size; 840 841 GLuint vs_start; 842 GLuint gs_start; 843 GLuint clip_start; 844 GLuint sf_start; 845 GLuint cs_start; 846 GLuint size; /* Hardware URB size, in KB. */ 847 848 /* gen6: True if the most recently sent _3DSTATE_URB message allocated 849 * URB space for the GS. 850 */ 851 bool gen6_gs_previously_active; 852 } urb; 853 854 855 /* BRW_NEW_CURBE_OFFSETS: 856 */ 857 struct { 858 GLuint wm_start; /**< pos of first wm const in CURBE buffer */ 859 GLuint wm_size; /**< number of float[4] consts, multiple of 16 */ 860 GLuint clip_start; 861 GLuint clip_size; 862 GLuint vs_start; 863 GLuint vs_size; 864 GLuint total_size; 865 866 drm_intel_bo *curbe_bo; 867 /** Offset within curbe_bo of space for current curbe entry */ 868 GLuint curbe_offset; 869 /** Offset within curbe_bo of space for next curbe entry */ 870 GLuint curbe_next_offset; 871 872 /** 873 * Copy of the last set of CURBEs uploaded. Frequently we'll end up 874 * in brw_curbe.c with the same set of constant data to be uploaded, 875 * so we'd rather not upload new constants in that case (it can cause 876 * a pipeline bubble since only up to 4 can be pipelined at a time). 877 */ 878 GLfloat *last_buf; 879 /** 880 * Allocation for where to calculate the next set of CURBEs. 881 * It's a hot enough path that malloc/free of that data matters. 882 */ 883 GLfloat *next_buf; 884 GLuint last_bufsz; 885 } curbe; 886 887 /** SAMPLER_STATE count and offset */ 888 struct { 889 GLuint count; 890 uint32_t offset; 891 } sampler; 892 893 struct { 894 struct brw_vs_prog_data *prog_data; 895 int8_t *constant_map; /* variable array following prog_data */ 896 897 drm_intel_bo *scratch_bo; 898 drm_intel_bo *const_bo; 899 /** Offset in the program cache to the VS program */ 900 uint32_t prog_offset; 901 uint32_t state_offset; 902 903 uint32_t push_const_offset; /* Offset in the batchbuffer */ 904 int push_const_size; /* in 256-bit register increments */ 905 906 /** @{ register allocator */ 907 908 struct ra_regs *regs; 909 910 /** 911 * Array of the ra classes for the unaligned contiguous register 912 * block sizes used. 913 */ 914 int *classes; 915 916 /** 917 * Mapping for register-allocated objects in *regs to the first 918 * GRF for that object. 919 */ 920 uint8_t *ra_reg_to_grf; 921 /** @} */ 922 923 uint32_t bind_bo_offset; 924 uint32_t surf_offset[BRW_MAX_VS_SURFACES]; 925 } vs; 926 927 struct { 928 struct brw_gs_prog_data *prog_data; 929 930 bool prog_active; 931 /** Offset in the program cache to the CLIP program pre-gen6 */ 932 uint32_t prog_offset; 933 uint32_t state_offset; 934 935 uint32_t bind_bo_offset; 936 uint32_t surf_offset[BRW_MAX_GS_SURFACES]; 937 } gs; 938 939 struct { 940 struct brw_clip_prog_data *prog_data; 941 942 /** Offset in the program cache to the CLIP program pre-gen6 */ 943 uint32_t prog_offset; 944 945 /* Offset in the batch to the CLIP state on pre-gen6. */ 946 uint32_t state_offset; 947 948 /* As of gen6, this is the offset in the batch to the CLIP VP, 949 * instead of vp_bo. 950 */ 951 uint32_t vp_offset; 952 } clip; 953 954 955 struct { 956 struct brw_sf_prog_data *prog_data; 957 958 /** Offset in the program cache to the CLIP program pre-gen6 */ 959 uint32_t prog_offset; 960 uint32_t state_offset; 961 uint32_t vp_offset; 962 } sf; 963 964 struct { 965 struct brw_wm_prog_data *prog_data; 966 struct brw_wm_compile *compile_data; 967 968 /** Input sizes, calculated from active vertex program. 969 * One bit per fragment program input attribute. 970 */ 971 GLbitfield input_size_masks[4]; 972 973 /** offsets in the batch to sampler default colors (texture border color) 974 */ 975 uint32_t sdc_offset[BRW_MAX_TEX_UNIT]; 976 977 GLuint render_surf; 978 979 drm_intel_bo *scratch_bo; 980 981 /** 982 * Buffer object used in place of multisampled null render targets on 983 * Gen6. See brw_update_null_renderbuffer_surface(). 984 */ 985 drm_intel_bo *multisampled_null_render_target_bo; 986 987 /** Offset in the program cache to the WM program */ 988 uint32_t prog_offset; 989 990 uint32_t state_offset; /* offset in batchbuffer to pre-gen6 WM state */ 991 992 drm_intel_bo *const_bo; /* pull constant buffer. */ 993 /** 994 * This is offset in the batch to the push constants on gen6. 995 * 996 * Pre-gen6, push constants live in the CURBE. 997 */ 998 uint32_t push_const_offset; 999 1000 /** Binding table of pointers to surf_bo entries */ 1001 uint32_t bind_bo_offset; 1002 uint32_t surf_offset[BRW_MAX_WM_SURFACES]; 1003 1004 /** @{ register allocator */ 1005 1006 struct ra_regs *regs; 1007 1008 /** Array of the ra classes for the unaligned contiguous 1009 * register block sizes used. 1010 */ 1011 int *classes; 1012 1013 /** 1014 * Mapping for register-allocated objects in *regs to the first 1015 * GRF for that object. 1016 */ 1017 uint8_t *ra_reg_to_grf; 1018 1019 /** 1020 * ra class for the aligned pairs we use for PLN, which doesn't 1021 * appear in *classes. 1022 */ 1023 int aligned_pairs_class; 1024 1025 /** @} */ 1026 } wm; 1027 1028 1029 struct { 1030 uint32_t state_offset; 1031 uint32_t blend_state_offset; 1032 uint32_t depth_stencil_state_offset; 1033 uint32_t vp_offset; 1034 } cc; 1035 1036 struct { 1037 struct brw_query_object *obj; 1038 drm_intel_bo *bo; 1039 int index; 1040 bool active; 1041 } query; 1042 /* Used to give every program string a unique id 1043 */ 1044 GLuint program_id; 1045 1046 int num_atoms; 1047 const struct brw_tracked_state **atoms; 1048 1049 /* If (INTEL_DEBUG & DEBUG_BATCH) */ 1050 struct { 1051 uint32_t offset; 1052 uint32_t size; 1053 enum state_struct_type type; 1054 } *state_batch_list; 1055 int state_batch_count; 1056 1057 struct brw_sol_state { 1058 uint32_t svbi_0_starting_index; 1059 uint32_t svbi_0_max_index; 1060 uint32_t offset_0_batch_start; 1061 uint32_t primitives_generated; 1062 uint32_t primitives_written; 1063 bool counting_primitives_generated; 1064 bool counting_primitives_written; 1065 } sol; 1066 1067 uint32_t render_target_format[MESA_FORMAT_COUNT]; 1068 bool format_supported_as_render_target[MESA_FORMAT_COUNT]; 1069 1070 /* PrimitiveRestart */ 1071 struct { 1072 bool in_progress; 1073 bool enable_cut_index; 1074 } prim_restart; 1075 1076 uint32_t num_instances; 1077 }; 1078 1079 1080 1081 #define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a) 1082 1083 struct brw_instruction_info { 1084 char *name; 1085 int nsrc; 1086 int ndst; 1087 bool is_arith; 1088 }; 1089 extern const struct brw_instruction_info brw_opcodes[128]; 1090 1091 /*====================================================================== 1092 * brw_vtbl.c 1093 */ 1094 void brwInitVtbl( struct brw_context *brw ); 1095 1096 /*====================================================================== 1097 * brw_context.c 1098 */ 1099 bool brwCreateContext(int api, 1100 const struct gl_config *mesaVis, 1101 __DRIcontext *driContextPriv, 1102 unsigned major_version, 1103 unsigned minor_version, 1104 uint32_t flags, 1105 unsigned *error, 1106 void *sharedContextPrivate); 1107 1108 /*====================================================================== 1109 * brw_queryobj.c 1110 */ 1111 void brw_init_queryobj_functions(struct dd_function_table *functions); 1112 void brw_prepare_query_begin(struct brw_context *brw); 1113 void brw_emit_query_begin(struct brw_context *brw); 1114 void brw_emit_query_end(struct brw_context *brw); 1115 1116 /*====================================================================== 1117 * brw_state_dump.c 1118 */ 1119 void brw_debug_batch(struct intel_context *intel); 1120 void brw_annotate_aub(struct intel_context *intel); 1121 1122 /*====================================================================== 1123 * brw_tex.c 1124 */ 1125 void brw_validate_textures( struct brw_context *brw ); 1126 1127 1128 /*====================================================================== 1129 * brw_program.c 1130 */ 1131 void brwInitFragProgFuncs( struct dd_function_table *functions ); 1132 1133 int brw_get_scratch_size(int size); 1134 void brw_get_scratch_bo(struct intel_context *intel, 1135 drm_intel_bo **scratch_bo, int size); 1136 1137 1138 /* brw_urb.c 1139 */ 1140 void brw_upload_urb_fence(struct brw_context *brw); 1141 1142 /* brw_curbe.c 1143 */ 1144 void brw_upload_cs_urb_state(struct brw_context *brw); 1145 1146 /* brw_disasm.c */ 1147 int brw_disasm (FILE *file, struct brw_instruction *inst, int gen); 1148 1149 /* brw_vs.c */ 1150 gl_clip_plane *brw_select_clip_planes(struct gl_context *ctx); 1151 1152 /* brw_wm_surface_state.c */ 1153 void brw_init_surface_formats(struct brw_context *brw); 1154 void 1155 brw_update_sol_surface(struct brw_context *brw, 1156 struct gl_buffer_object *buffer_obj, 1157 uint32_t *out_offset, unsigned num_vector_components, 1158 unsigned stride_dwords, unsigned offset_dwords); 1159 void brw_upload_ubo_surfaces(struct brw_context *brw, 1160 struct gl_shader *shader, 1161 uint32_t *surf_offsets); 1162 1163 /* gen6_sol.c */ 1164 void 1165 brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode, 1166 struct gl_transform_feedback_object *obj); 1167 void 1168 brw_end_transform_feedback(struct gl_context *ctx, 1169 struct gl_transform_feedback_object *obj); 1170 1171 /* gen7_sol_state.c */ 1172 void 1173 gen7_end_transform_feedback(struct gl_context *ctx, 1174 struct gl_transform_feedback_object *obj); 1175 1176 /* brw_blorp_blit.cpp */ 1177 GLbitfield 1178 brw_blorp_framebuffer(struct intel_context *intel, 1179 GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, 1180 GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, 1181 GLbitfield mask, GLenum filter); 1182 1183 /* gen6_multisample_state.c */ 1184 void 1185 gen6_emit_3dstate_multisample(struct brw_context *brw, 1186 unsigned num_samples); 1187 void 1188 gen6_emit_3dstate_sample_mask(struct brw_context *brw, 1189 unsigned num_samples, float coverage, 1190 bool coverage_invert); 1191 1192 /* gen7_urb.c */ 1193 void 1194 gen7_allocate_push_constants(struct brw_context *brw); 1195 1196 void 1197 gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries, 1198 GLuint vs_size, GLuint vs_start); 1199 1200 1201 1202 /*====================================================================== 1203 * Inline conversion functions. These are better-typed than the 1204 * macros used previously: 1205 */ 1206 static INLINE struct brw_context * 1207 brw_context( struct gl_context *ctx ) 1208 { 1209 return (struct brw_context *)ctx; 1210 } 1211 1212 static INLINE struct brw_vertex_program * 1213 brw_vertex_program(struct gl_vertex_program *p) 1214 { 1215 return (struct brw_vertex_program *) p; 1216 } 1217 1218 static INLINE const struct brw_vertex_program * 1219 brw_vertex_program_const(const struct gl_vertex_program *p) 1220 { 1221 return (const struct brw_vertex_program *) p; 1222 } 1223 1224 static INLINE struct brw_fragment_program * 1225 brw_fragment_program(struct gl_fragment_program *p) 1226 { 1227 return (struct brw_fragment_program *) p; 1228 } 1229 1230 static INLINE const struct brw_fragment_program * 1231 brw_fragment_program_const(const struct gl_fragment_program *p) 1232 { 1233 return (const struct brw_fragment_program *) p; 1234 } 1235 1236 /** 1237 * Pre-gen6, the register file of the EUs was shared between threads, 1238 * and each thread used some subset allocated on a 16-register block 1239 * granularity. The unit states wanted these block counts. 1240 */ 1241 static inline int 1242 brw_register_blocks(int reg_count) 1243 { 1244 return ALIGN(reg_count, 16) / 16 - 1; 1245 } 1246 1247 static inline uint32_t 1248 brw_program_reloc(struct brw_context *brw, uint32_t state_offset, 1249 uint32_t prog_offset) 1250 { 1251 struct intel_context *intel = &brw->intel; 1252 1253 if (intel->gen >= 5) { 1254 /* Using state base address. */ 1255 return prog_offset; 1256 } 1257 1258 drm_intel_bo_emit_reloc(intel->batch.bo, 1259 state_offset, 1260 brw->cache.bo, 1261 prog_offset, 1262 I915_GEM_DOMAIN_INSTRUCTION, 0); 1263 1264 return brw->cache.bo->offset + prog_offset; 1265 } 1266 1267 bool brw_do_cubemap_normalize(struct exec_list *instructions); 1268 bool brw_lower_texture_gradients(struct exec_list *instructions); 1269 1270 #ifdef __cplusplus 1271 } 1272 #endif 1273 1274 #endif 1275
