1 /*---------------------------------------------------------------*/ 2 /*--- begin guest_tilegx_helpers.c ---*/ 3 /*---------------------------------------------------------------*/ 4 5 /* 6 This file is part of Valgrind, a dynamic binary instrumentation 7 framework. 8 9 Copyright (C) 2010-2015 Tilera Corp. 10 11 This program is free software; you can redistribute it and/or 12 modify it under the terms of the GNU General Public License as 13 published by the Free Software Foundation; either version 2 of the 14 License, or (at your option) any later version. 15 16 This program is distributed in the hope that it will be useful, but 17 WITHOUT ANY WARRANTY; without even the implied warranty of 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 General Public License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software 23 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 24 02111-1307, USA. 25 26 The GNU General Public License is contained in the file COPYING. 27 */ 28 29 /* Contributed by Zhi-Gang Liu <zliu at tilera dot com> */ 30 31 #include "libvex_basictypes.h" 32 #include "libvex_emnote.h" 33 #include "libvex_guest_tilegx.h" 34 #include "libvex_ir.h" 35 #include "libvex.h" 36 37 #include "main_util.h" 38 #include "guest_generic_bb_to_IR.h" 39 #include "guest_tilegx_defs.h" 40 41 /* This file contains helper functions for tilegx guest code. Calls to 42 these functions are generated by the back end. 43 */ 44 45 #define ALWAYSDEFD(field) \ 46 { offsetof(VexGuestTILEGXState, field), \ 47 (sizeof ((VexGuestTILEGXState*)0)->field) } 48 49 IRExpr *guest_tilegx_spechelper ( const HChar * function_name, IRExpr ** args, 50 IRStmt ** precedingStmts, Int n_precedingStmts) 51 { 52 return NULL; 53 } 54 55 /* VISIBLE TO LIBVEX CLIENT */ 56 void LibVEX_GuestTILEGX_initialise ( VexGuestTILEGXState * vex_state ) 57 { 58 vex_state->guest_r0 = 0; 59 vex_state->guest_r1 = 0; 60 vex_state->guest_r2 = 0; 61 vex_state->guest_r3 = 0; 62 vex_state->guest_r4 = 0; 63 vex_state->guest_r5 = 0; 64 vex_state->guest_r6 = 0; 65 vex_state->guest_r7 = 0; 66 vex_state->guest_r8 = 0; 67 vex_state->guest_r9 = 0; 68 vex_state->guest_r10 = 0; 69 vex_state->guest_r11 = 0; 70 vex_state->guest_r12 = 0; 71 vex_state->guest_r13 = 0; 72 vex_state->guest_r14 = 0; 73 vex_state->guest_r15 = 0; 74 vex_state->guest_r16 = 0; 75 vex_state->guest_r17 = 0; 76 vex_state->guest_r18 = 0; 77 vex_state->guest_r19 = 0; 78 vex_state->guest_r20 = 0; 79 vex_state->guest_r21 = 0; 80 vex_state->guest_r22 = 0; 81 vex_state->guest_r23 = 0; 82 vex_state->guest_r24 = 0; 83 vex_state->guest_r25 = 0; 84 vex_state->guest_r26 = 0; 85 vex_state->guest_r27 = 0; 86 vex_state->guest_r28 = 0; 87 vex_state->guest_r29 = 0; 88 vex_state->guest_r30 = 0; 89 vex_state->guest_r31 = 0; 90 vex_state->guest_r32 = 0; 91 vex_state->guest_r33 = 0; 92 vex_state->guest_r34 = 0; 93 vex_state->guest_r35 = 0; 94 vex_state->guest_r36 = 0; 95 vex_state->guest_r37 = 0; 96 vex_state->guest_r38 = 0; 97 vex_state->guest_r39 = 0; 98 vex_state->guest_r40 = 0; 99 vex_state->guest_r41 = 0; 100 vex_state->guest_r42 = 0; 101 vex_state->guest_r43 = 0; 102 vex_state->guest_r44 = 0; 103 vex_state->guest_r45 = 0; 104 vex_state->guest_r46 = 0; 105 vex_state->guest_r47 = 0; 106 vex_state->guest_r48 = 0; 107 vex_state->guest_r49 = 0; 108 vex_state->guest_r50 = 0; 109 vex_state->guest_r51 = 0; 110 vex_state->guest_r52 = 0; 111 vex_state->guest_r53 = 0; 112 vex_state->guest_r54 = 0; 113 vex_state->guest_r55 = 0; 114 115 vex_state->guest_pc = 0; /* Program counter */ 116 117 vex_state->guest_EMNOTE = 0; 118 vex_state->guest_CMSTART = 0; 119 120 /* For clflush: record start and length of area to invalidate */ 121 vex_state->guest_CMSTART = 0; 122 vex_state->guest_CMLEN = 0; 123 124 /* Used to record the unredirected guest address at the start of 125 a translation whose start has been redirected. By reading 126 this pseudo-register shortly afterwards, the translation can 127 find out what the corresponding no-redirection address was. 128 Note, this is only set for wrap-style redirects, not for 129 replace-style ones. */ 130 vex_state->guest_NRADDR = 0; 131 } 132 133 /*-----------------------------------------------------------*/ 134 /*--- Describing the tilegx guest state, for the benefit ---*/ 135 /*--- of iropt and instrumenters. ---*/ 136 /*-----------------------------------------------------------*/ 137 138 /* Figure out if any part of the guest state contained in minoff 139 .. maxoff requires precise memory exceptions. If in doubt return 140 True (but this is generates significantly slower code). 141 142 We enforce precise exns for guest SP, PC. 143 */ 144 Bool guest_tilegx_state_requires_precise_mem_exns ( 145 Int minoff, Int maxoff, 146 VexRegisterUpdates pxControl) 147 { 148 Int sp_min = offsetof(VexGuestTILEGXState, guest_r54); 149 Int sp_max = sp_min + 8 - 1; 150 Int pc_min = offsetof(VexGuestTILEGXState, guest_pc); 151 Int pc_max = pc_min + 8 - 1; 152 153 if (maxoff < sp_min || minoff > sp_max) { 154 /* no overlap with sp */ 155 if (pxControl == VexRegUpdSpAtMemAccess) 156 return False; /* We only need to check stack pointer. */ 157 } else { 158 return True; 159 } 160 161 if (maxoff < pc_min || minoff > pc_max) { 162 /* no overlap with pc */ 163 } else { 164 return True; 165 } 166 167 /* We appear to need precise updates of R52 in order to get proper 168 stacktraces from non-optimised code. */ 169 Int fp_min = offsetof(VexGuestTILEGXState, guest_r52); 170 Int fp_max = fp_min + 8 - 1; 171 172 if (maxoff < fp_min || minoff > fp_max) { 173 /* no overlap with fp */ 174 } else { 175 return True; 176 } 177 178 return False; 179 } 180 181 VexGuestLayout tilegxGuest_layout = { 182 /* Total size of the guest state, in bytes. */ 183 .total_sizeB = sizeof(VexGuestTILEGXState), 184 /* Describe the stack pointer. */ 185 .offset_SP = offsetof(VexGuestTILEGXState, guest_r54), 186 .sizeof_SP = 8, 187 /* Describe the frame pointer. */ 188 .offset_FP = offsetof(VexGuestTILEGXState, guest_r52), 189 .sizeof_FP = 8, 190 /* Describe the instruction pointer. */ 191 .offset_IP = offsetof(VexGuestTILEGXState, guest_pc), 192 .sizeof_IP = 8, 193 /* Describe any sections to be regarded by Memcheck as 194 'always-defined'. */ 195 .n_alwaysDefd = 8, 196 /* ? :( */ 197 .alwaysDefd = { 198 /* 0 */ ALWAYSDEFD(guest_r0), 199 /* 1 */ ALWAYSDEFD(guest_r1), 200 /* 2 */ ALWAYSDEFD(guest_EMNOTE), 201 /* 3 */ ALWAYSDEFD(guest_CMSTART), 202 /* 4 */ ALWAYSDEFD(guest_CMLEN), 203 /* 5 */ ALWAYSDEFD(guest_r52), 204 /* 6 */ ALWAYSDEFD(guest_r55), 205 /* 7 */ ALWAYSDEFD(guest_pc), 206 } 207 }; 208 209 #ifdef __tilegx__ 210 ULong tilegx_dirtyhelper_gen ( ULong opc, 211 ULong rd0, ULong rd1, 212 ULong rd2, ULong rd3) 213 { 214 switch (opc) 215 { 216 case 0: 217 { 218 /* break point */ 219 switch (rd0) { 220 case 0x286a44ae90048fffULL: 221 asm (" bpt "); 222 break; 223 default: 224 vex_printf("unhandled \"bpt\": cins=%016llx\n", rd0); 225 226 vassert(0); 227 return 0; 228 } 229 } 230 break; 231 case 28: 232 { 233 return __insn_addxsc(rd1, rd2); 234 } 235 break; 236 237 case 150: 238 { 239 __insn_mf(); 240 return 0; 241 } 242 break; 243 244 case 152: /* mm rd, ra, imm0, imm1 */ 245 { 246 ULong mask; 247 248 if( rd2 <= rd3) 249 mask = (-1ULL << rd2) ^ ((-1ULL << rd3) << 1); 250 else 251 mask = (-1ULL << rd2) | (-1ULL >> (63 - rd3)); 252 253 return (rd0 & mask) | (rd1 & (-1ULL ^ mask)); 254 } 255 break; 256 case 154: /* mtspr imm, ra */ 257 { 258 switch(rd0) 259 { 260 case 0x2785: 261 __insn_mtspr(0x2785, rd1); 262 break; 263 case 0x2780: 264 __insn_mtspr(0x2780, rd1); 265 break; 266 case 0x2708: 267 __insn_mtspr(0x2708, rd1); 268 break; 269 case 0x2580: 270 __insn_mtspr(0x2580, rd1); 271 break; 272 case 0x2581: 273 __insn_mtspr(0x2581, rd1); 274 break; 275 case 0x2709: // PASS 276 __insn_mtspr(0x2709, rd1); 277 break; 278 case 0x2707: // FAIL 279 __insn_mtspr(0x2707, rd1); 280 break; 281 case 0x2705: // DONE 282 __insn_mtspr(0x2705, rd1); 283 break; 284 285 case 0x2870: // 286 287 default: 288 vex_printf("opc=%d rd0=%llx rd1=%llx\n", 289 (int)opc, rd0, rd1); 290 vassert(0); 291 } 292 } 293 break; 294 295 case 151: /* mfspr rd, imm */ 296 { 297 switch(rd1) 298 { 299 case 0x2785: // SIM_CTRL 300 return __insn_mfspr(0x2785); 301 break; 302 303 case 0x2708: // ICS 304 return __insn_mfspr(0x2708); 305 break; 306 307 case 0x2780: // CMPEXCH_VALUE 308 return __insn_mfspr(0x2780); 309 break; 310 311 case 0x2781: // CYCLE 312 return __insn_mfspr(0x2781); 313 break; 314 315 case 0x2709: // PASS 316 return __insn_mfspr(0x2709); 317 break; 318 319 case 0x2707: // FAIL 320 return __insn_mfspr(0x2707); 321 break; 322 323 case 0x2705: // DONE 324 return __insn_mfspr(0x2705); 325 break; 326 327 case 0x2580: // EX_CONTEXT_0 328 return __insn_mfspr(0x2580); 329 break; 330 331 case 0x2581: // EX_CONTEXT_1 332 return __insn_mfspr(0x2581); 333 break; 334 335 default: 336 vex_printf("opc=%d rd0=%llx rd1=%llx\n", 337 (int)opc, rd0, rd1); 338 vassert(0); 339 } 340 } 341 break; 342 case 183: 343 { 344 return __insn_pcnt(rd1); 345 } 346 break; 347 case 184: 348 { 349 return __insn_revbits(rd1); 350 } 351 break; 352 case 185: /* revbytes rd, ra */ 353 { 354 return __insn_revbytes(rd1); 355 } 356 break; 357 358 case 102: 359 return __insn_fsingle_add1(rd1, rd2); 360 break; 361 362 case 103: 363 return __insn_fsingle_addsub2(rd0, rd1, rd2); 364 break; 365 366 case 104: 367 return __insn_fsingle_mul1(rd1, rd2); 368 break; 369 370 case 105: 371 return __insn_fsingle_mul2(rd1, rd2); 372 break; 373 374 case 106: 375 return __insn_fsingle_pack1(rd1); 376 break; 377 378 case 107: 379 return __insn_fsingle_pack2(rd1, rd2); 380 break; 381 382 case 108: 383 return __insn_fsingle_sub1(rd1, rd2); 384 break; 385 386 case 21: 387 switch (rd0) { 388 case 0x286a44ae90048fffULL: 389 asm ("{ moveli zero, 72 ; raise }"); 390 break; 391 default: 392 vex_printf("unhandled \"raise\": cins=%016llx\n", rd0); 393 __insn_ill(); 394 return 0; 395 } 396 break; 397 398 case 64: 399 { 400 return __insn_cmul(rd1, rd2); 401 } 402 break; 403 case 65: 404 { 405 return __insn_cmula(rd0, rd1, rd2); 406 } 407 break; 408 case 66: 409 { 410 return __insn_cmulaf(rd0, rd1, rd2); 411 } 412 break; 413 case 67: 414 { 415 return __insn_cmulf(rd1, rd2); 416 } 417 break; 418 case 68: 419 { 420 return __insn_cmulfr(rd1, rd2); 421 } 422 break; 423 case 69: 424 { 425 return __insn_cmulh(rd1, rd2); 426 } 427 break; 428 case 70: 429 { 430 return __insn_cmulhr(rd1, rd2); 431 } 432 break; 433 case 71: 434 { 435 return __insn_crc32_32(rd1, rd2); 436 } 437 break; 438 case 72: 439 { 440 return __insn_crc32_8(rd1, rd2); 441 } 442 break; 443 case 75: 444 { 445 return __insn_dblalign2(rd1, rd2); 446 } 447 break; 448 case 76: 449 { 450 return __insn_dblalign4(rd1, rd2); 451 } 452 break; 453 case 77: 454 { 455 return __insn_dblalign6(rd1, rd2); 456 } 457 break; 458 case 78: 459 { 460 __insn_drain(); 461 return 0; 462 } 463 break; 464 case 79: 465 { 466 __insn_dtlbpr(rd0); 467 return 0; 468 } 469 break; 470 case 82: 471 { 472 return __insn_fdouble_add_flags(rd1, rd2); 473 } 474 break; 475 case 83: 476 { 477 return __insn_fdouble_addsub(rd0, rd1, rd2); 478 } 479 break; 480 case 84: 481 { 482 return __insn_fdouble_mul_flags(rd1, rd2); 483 } 484 break; 485 case 85: 486 { 487 return __insn_fdouble_pack1(rd1, rd2); 488 } 489 break; 490 case 86: 491 { 492 return __insn_fdouble_pack2(rd0, rd1, rd2); 493 } 494 break; 495 case 87: 496 { 497 return __insn_fdouble_sub_flags(rd1, rd2); 498 } 499 break; 500 case 88: 501 { 502 return __insn_fdouble_unpack_max(rd1, rd2); 503 } 504 break; 505 case 89: 506 { 507 return __insn_fdouble_unpack_min(rd1, rd2); 508 } 509 break; 510 511 case 98: 512 { 513 __insn_finv(rd0); 514 return 0; 515 } 516 break; 517 case 99: 518 { 519 __insn_flush(rd0); 520 return 0; 521 } 522 break; 523 case 100: 524 { 525 __insn_flushwb(); 526 return 0; 527 } 528 break; 529 530 case 109: 531 { 532 __insn_icoh((ULong *)rd0); 533 return 0; 534 } 535 break; 536 case 110: 537 { 538 __insn_ill(); 539 } 540 break; 541 case 111: 542 { 543 __insn_inv((ULong *)rd0); 544 return 0; 545 } 546 break; 547 548 case 169: 549 { 550 return __insn_mula_hu_hu(rd0, rd1, rd2); 551 } 552 break; 553 case 170: 554 { 555 return __insn_mula_hu_ls(rd0, rd1, rd2); 556 } 557 break; 558 case 205: 559 { 560 return __insn_shufflebytes(rd0, rd1, rd2); 561 } 562 break; 563 case 224: 564 { 565 return __insn_subxsc(rd1, rd2); 566 } 567 break; 568 case 229: 569 { 570 return __insn_tblidxb0(rd0, rd1); 571 } 572 break; 573 case 230: 574 { 575 return __insn_tblidxb1(rd0, rd1); 576 } 577 break; 578 case 231: 579 { 580 return __insn_tblidxb2(rd0, rd1); 581 } 582 break; 583 case 232: 584 { 585 return __insn_tblidxb3(rd0, rd1); 586 } 587 break; 588 case 233: 589 { 590 return __insn_v1add(rd1, rd2); 591 } 592 break; 593 case 234: 594 { 595 return __insn_v1add(rd1, rd2); 596 } 597 break; 598 case 235: 599 { 600 return __insn_v1adduc(rd1, rd2); 601 } 602 break; 603 case 236: 604 { 605 return __insn_v1adiffu(rd1, rd2); 606 } 607 break; 608 case 237: 609 { 610 return __insn_v1avgu(rd1, rd2); 611 } 612 break; 613 614 case 238: 615 { 616 return __insn_v1cmpeq(rd1, rd2); 617 } 618 break; 619 case 239: 620 { 621 return __insn_v1cmpeq(rd1, rd2); 622 } 623 break; 624 case 240: 625 { 626 return __insn_v1cmples(rd1, rd2); 627 } 628 break; 629 case 241: 630 { 631 return __insn_v1cmpleu(rd1, rd2); 632 } 633 break; 634 case 242: 635 { 636 return __insn_v1cmplts(rd1, rd2); 637 } 638 break; 639 case 243: 640 { 641 return __insn_v1cmplts(rd1, rd2); 642 } 643 break; 644 case 244: 645 { 646 return __insn_v1cmpltu(rd1, rd2); 647 } 648 break; 649 case 245: 650 { 651 return __insn_v1cmpltu(rd1, rd2); 652 } 653 break; 654 case 246: 655 { 656 return __insn_v1cmpne(rd1, rd2); 657 } 658 break; 659 case 247: 660 { 661 return __insn_v1ddotpu(rd1, rd2); 662 } 663 break; 664 case 248: 665 { 666 return __insn_v1ddotpua(rd0, rd1, rd2); 667 } 668 break; 669 case 249: 670 { 671 return __insn_v1ddotpus(rd1, rd2); 672 } 673 break; 674 case 250: 675 { 676 return __insn_v1ddotpusa(rd0, rd1, rd2); 677 } 678 break; 679 case 251: 680 { 681 return __insn_v1dotp(rd1, rd2); 682 } 683 break; 684 case 252: 685 { 686 return __insn_v1dotpa(rd0, rd1, rd2); 687 } 688 break; 689 case 253: 690 { 691 return __insn_v1dotpu(rd1, rd2); 692 } 693 break; 694 case 254: 695 { 696 return __insn_v1dotpua(rd0, rd1, rd2); 697 } 698 break; 699 case 255: 700 { 701 return __insn_v1dotpus(rd1, rd2); 702 } 703 break; 704 case 256: 705 { 706 return __insn_v1dotpusa(rd0, rd1, rd2); 707 } 708 break; 709 case 257: 710 { 711 return __insn_v1int_h(rd1, rd2); 712 } 713 break; 714 case 258: 715 { 716 return __insn_v1int_l(rd1, rd2); 717 } 718 break; 719 case 259: 720 { 721 return __insn_v1maxu(rd1, rd2); 722 } 723 break; 724 case 260: 725 { 726 return __insn_v1maxu(rd1, rd2); 727 } 728 break; 729 case 261: 730 { 731 return __insn_v1minu(rd1, rd2); 732 } 733 break; 734 case 262: 735 { 736 return __insn_v1minu(rd1, rd2); 737 } 738 break; 739 case 263: 740 { 741 return __insn_v1mnz(rd1, rd2); 742 } 743 break; 744 case 264: 745 { 746 return __insn_v1multu(rd1, rd2); 747 } 748 break; 749 case 265: 750 { 751 return __insn_v1mulu(rd1, rd2); 752 } 753 break; 754 case 266: 755 { 756 return __insn_v1mulus(rd1, rd2); 757 } 758 break; 759 case 267: 760 { 761 return __insn_v1mz(rd1, rd2); 762 } 763 break; 764 case 268: 765 { 766 return __insn_v1sadau(rd0, rd1, rd2); 767 } 768 break; 769 case 269: 770 { 771 return __insn_v1sadu(rd1, rd2); 772 } 773 break; 774 case 270: 775 { 776 return __insn_v1shl(rd1, rd2); 777 } 778 break; 779 case 271: 780 { 781 return __insn_v1shl(rd1, rd2); 782 } 783 break; 784 case 272: 785 { 786 return __insn_v1shrs(rd1, rd2); 787 } 788 break; 789 case 273: 790 { 791 return __insn_v1shrs(rd1, rd2); 792 } 793 break; 794 case 274: 795 { 796 return __insn_v1shru(rd1, rd2); 797 } 798 break; 799 case 275: 800 { 801 return __insn_v1shrui(rd1, rd2); 802 } 803 break; 804 case 276: 805 { 806 return __insn_v1sub(rd1, rd2); 807 } 808 break; 809 case 277: 810 { 811 return __insn_v1subuc(rd1, rd2); 812 } 813 break; 814 case 278: 815 { 816 return __insn_v2add(rd1, rd2); 817 } 818 break; 819 case 279: 820 { 821 return __insn_v2add(rd1, rd2); 822 } 823 break; 824 case 280: 825 { 826 return __insn_v2addsc(rd1, rd2); 827 } 828 break; 829 case 281: 830 { 831 return __insn_v2adiffs(rd1, rd2); 832 } 833 break; 834 case 282: 835 { 836 return __insn_v2avgs(rd1, rd2); 837 } 838 break; 839 case 283: 840 { 841 return __insn_v2cmpeq(rd1, rd2); 842 } 843 break; 844 case 284: 845 { 846 return __insn_v2cmpeq(rd1, rd2); 847 } 848 break; 849 case 285: 850 { 851 return __insn_v2cmples(rd1, rd2); 852 } 853 break; 854 case 286: 855 { 856 return __insn_v2cmpleu(rd1, rd2); 857 } 858 break; 859 case 287: 860 { 861 return __insn_v2cmplts(rd1, rd2); 862 } 863 break; 864 case 288: 865 { 866 return __insn_v2cmplts(rd1, rd2); 867 } 868 break; 869 case 289: 870 { 871 return __insn_v2cmpltu(rd1, rd2); 872 } 873 break; 874 case 290: 875 { 876 return __insn_v2cmpltu(rd1, rd2); 877 } 878 break; 879 case 291: 880 { 881 return __insn_v2cmpne(rd1, rd2); 882 } 883 break; 884 case 292: 885 { 886 return __insn_v2dotp(rd1, rd2); 887 } 888 break; 889 case 293: 890 { 891 return __insn_v2dotpa(rd0, rd1, rd2); 892 } 893 break; 894 case 294: 895 { 896 return __insn_v2int_h(rd1, rd2); 897 } 898 break; 899 case 295: 900 { 901 return __insn_v2int_l(rd1, rd2); 902 } 903 break; 904 case 296: 905 { 906 return __insn_v2maxs(rd1, rd2); 907 } 908 break; 909 case 297: 910 { 911 return __insn_v2maxs(rd1, rd2); 912 } 913 break; 914 case 298: 915 { 916 return __insn_v2mins(rd1, rd2); 917 } 918 break; 919 case 299: 920 { 921 return __insn_v2mins(rd1, rd2); 922 } 923 break; 924 case 300: 925 { 926 return __insn_v2mnz(rd1, rd2); 927 } 928 break; 929 case 301: 930 { 931 return __insn_v2mulfsc(rd1, rd2); 932 } 933 break; 934 case 302: 935 { 936 return __insn_v2muls(rd1, rd2); 937 } 938 break; 939 case 303: 940 { 941 return __insn_v2mults(rd1, rd2); 942 } 943 break; 944 case 304: 945 { 946 return __insn_v2mz(rd1, rd2); 947 } 948 break; 949 case 305: 950 { 951 return __insn_v2packh(rd1, rd2); 952 } 953 break; 954 case 306: 955 { 956 return __insn_v2packl(rd1, rd2); 957 } 958 break; 959 case 307: 960 { 961 return __insn_v2packuc(rd1, rd2); 962 } 963 break; 964 case 308: 965 { 966 return __insn_v2sadas(rd0, rd1, rd2); 967 } 968 break; 969 case 309: 970 { 971 return __insn_v2sadau(rd0, rd1, rd2); 972 } 973 break; 974 case 310: 975 { 976 return __insn_v2sads(rd1, rd2); 977 } 978 break; 979 case 311: 980 { 981 return __insn_v2sadu(rd1, rd2); 982 } 983 break; 984 case 312: 985 { 986 return __insn_v2shl(rd1, rd2); 987 } 988 break; 989 case 313: 990 { 991 return __insn_v2shl(rd1, rd2); 992 } 993 break; 994 case 314: 995 { 996 return __insn_v2shlsc(rd1, rd2); 997 } 998 break; 999 case 315: 1000 { 1001 return __insn_v2shrs(rd1, rd2); 1002 } 1003 break; 1004 case 316: 1005 { 1006 return __insn_v2shrs(rd1, rd2); 1007 } 1008 break; 1009 case 317: 1010 { 1011 return __insn_v2shru(rd1, rd2); 1012 } 1013 break; 1014 case 318: 1015 { 1016 return __insn_v2shru(rd1, rd2); 1017 } 1018 break; 1019 case 319: 1020 { 1021 return __insn_v2sub(rd1, rd2); 1022 } 1023 break; 1024 case 320: 1025 { 1026 return __insn_v2subsc(rd1, rd2); 1027 } 1028 break; 1029 case 321: 1030 { 1031 return __insn_v4add(rd1, rd2); 1032 } 1033 break; 1034 case 322: 1035 { 1036 return __insn_v4addsc(rd1, rd2); 1037 } 1038 break; 1039 case 323: 1040 { 1041 return __insn_v4int_h(rd1, rd2); 1042 } 1043 break; 1044 case 324: 1045 { 1046 return __insn_v4int_l(rd1, rd2); 1047 } 1048 break; 1049 case 325: 1050 { 1051 return __insn_v4packsc(rd1, rd2); 1052 } 1053 break; 1054 case 326: 1055 { 1056 return __insn_v4shl(rd1, rd2); 1057 } 1058 break; 1059 case 327: 1060 { 1061 return __insn_v4shlsc(rd1, rd2); 1062 } 1063 break; 1064 case 328: 1065 { 1066 return __insn_v4shrs(rd1, rd2); 1067 } 1068 break; 1069 case 329: 1070 { 1071 return __insn_v4shru(rd1, rd2); 1072 } 1073 break; 1074 case 330: 1075 { 1076 return __insn_v4sub(rd1, rd2); 1077 } 1078 break; 1079 case 331: 1080 { 1081 return __insn_v4subsc(rd1, rd2); 1082 } 1083 break; 1084 1085 default: 1086 vex_printf("opc=%d rd0=%llx rd1=%llx\n", 1087 (int)opc, rd0, rd1); 1088 vassert(0); 1089 } 1090 } 1091 #else 1092 ULong tilegx_dirtyhelper_gen ( ULong opc, 1093 ULong rd0, ULong rd1, 1094 ULong rd2, ULong rd3 ) 1095 { 1096 vex_printf("NOT a TILEGX platform"); 1097 return 0; 1098 } 1099 #endif /* __tilegx__ */ 1100 1101 /*---------------------------------------------------------------*/ 1102 /*--- end guest_tilegx_helpers.c ---*/ 1103 /*---------------------------------------------------------------*/ 1104
