/external/llvm/lib/Target/Hexagon/ |
HexagonExpandPredSpillCode.cpp | 104 MachineOperand &Op3 = MI->getOperand(3); // Modifier value. 108 Hexagon::C6)->addOperand(Op3); 226 MachineOperand &Op3 = MI->getOperand(3); // Modifier value. 229 Hexagon::C6)->addOperand(Op3);
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HexagonSplitDouble.cpp | 880 MachineOperand &Op3 = MI->getOperand(3); 881 assert(Op0.isReg() && Op1.isReg() && Op2.isReg() && Op3.isImm()); 882 int64_t Sh64 = Op3.getImm(); 902 // Op0 = S2_asl_i_p_or Op1, Op2, Op3 903 // means: Op0 = or (Op1, asl(Op2, Op3)) [all...] |
HexagonInstrInfo.cpp | [all...] |
/external/llvm/lib/Target/XCore/Disassembler/ |
XCoreDisassembler.cpp | 260 unsigned &Op3) { 270 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); 539 unsigned Op1, Op2, Op3; 540 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 544 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 552 unsigned Op1, Op2, Op3; 553 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 557 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 565 unsigned Op1, Op2, Op3; 566 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); [all...] |
/external/llvm/lib/Target/AArch64/InstPrinter/ |
AArch64InstPrinter.cpp | 69 const MCOperand &Op3 = MI->getOperand(3); 73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { 76 switch (Op3.getImm()) { 109 if (Op2.isImm() && Op3.isImm()) { 113 int64_t imms = Op3.getImm(); 143 if (Op2.getImm() > Op3.getImm()) { 146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; 154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeIntegerTypes.cpp | 231 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); 236 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(), [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |